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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- mux for use in the montgommery multiplier systolic array ----
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---- 1-bit mux for a standard cell in the montgommery ----
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---- multiplier systolic array ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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-- 1-bit mux for a standard cell in the montgommery multiplier systolic array
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entity cell_1b_mux is
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entity cell_1b_mux is
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port (
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port (
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-- input bits
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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m : in std_logic;
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m : in std_logic;
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-- selection bits
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- mux out
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result : out std_logic
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result : out std_logic
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);
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);
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end cell_1b_mux;
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end cell_1b_mux;
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architecture Behavioral of cell_1b_mux is
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architecture Behavioral of cell_1b_mux is
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signal sel : std_logic_vector(1 downto 0);
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signal sel : std_logic_vector(1 downto 0);
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begin
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begin
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-- selection bits
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sel <= x & q;
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sel <= x & q;
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-- multipexer
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with sel select
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with sel select
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result <= my when "11",
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result <= my when "11",
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y when "10",
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y when "10",
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m when "01",
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m when "01",
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'0' when others;
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'0' when others;
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