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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [counter_sync.vhd] - Diff between revs 3 and 19

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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
 
-- counter with synchronous count enable. It generates an
 
-- overflow when max_value is reached
entity counter_sync is
entity counter_sync is
  generic(
  generic(
    max_value : integer := 1024
    max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
  );
  );
  port(
  port(
    reset_value : in integer;
    reset_value : in integer;   -- value the counter counts to
    core_clk    : in std_logic;
    core_clk    : in std_logic; -- clock input
    ce          : in std_logic;
    ce          : in std_logic; -- count enable
    reset       : in std_logic;
    reset       : in std_logic; -- reset input
    overflow    : out std_logic
    overflow    : out std_logic -- gets high when counter reaches reset_value
  );
  );
end counter_sync;
end counter_sync;
 
 
 
 
architecture Behavioral of counter_sync is
architecture Behavioral of counter_sync is
 
 
        signal overflow_i : std_logic := '0';
 
begin
begin
 
 
        overflow <= overflow_i;
        -- counter process with asynchronous active high reset
 
        count_proc: process(core_clk, ce, reset)
        COUNT_PROC: process(core_clk, ce, reset)
                variable steps_counter : integer range 0 to max_value-1;
                variable steps_counter : integer range 0 to max_value-1 := 0;
 
        begin
        begin
                if reset = '1' then  -- reset counter
                if reset = '1' then  -- reset counter
                        steps_counter := 0;
                        steps_counter := 0;
                        overflow_i <= '0';
                        overflow <= '0';
                elsif rising_edge(core_clk) then
                elsif rising_edge(core_clk) then
                        if ce = '1' then -- count
                        -- counter is enabled, count till reset_value
 
                        if ce = '1' then
                                if steps_counter = (reset_value-1) then -- generate overflow and reset counter
                                if steps_counter = (reset_value-1) then -- generate overflow and reset counter
                                        steps_counter := 0;
                                        steps_counter := 0;
                                        overflow_i <= '1';
                                        overflow <= '1';
                                else    -- just count
                                else    -- just count
                                        steps_counter := steps_counter + 1;
                                        steps_counter := steps_counter + 1;
                                        overflow_i <= '0';
                                        overflow <= '0';
                                end if;
                                end if;
                        else
                        else
                                overflow_i <= '0';
                        --counter disabled, halt counter
 
                                overflow <= '0';
                                steps_counter := steps_counter;
                                steps_counter := steps_counter;
                        end if;
                        end if;
                end if;
                end if;
        end process;
        end process;
 
 
end Behavioral;
end Behavioral;
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