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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [counter_sync.vhd] - Diff between revs 19 and 39

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Rev 19 Rev 39
Line 65... Line 65...
 
 
architecture Behavioral of counter_sync is
architecture Behavioral of counter_sync is
begin
begin
 
 
        -- counter process with asynchronous active high reset
        -- counter process with asynchronous active high reset
        count_proc: process(core_clk, ce, reset)
        count_proc: process(core_clk, reset)
                variable steps_counter : integer range 0 to max_value-1;
                variable steps_counter : integer range 0 to max_value-1;
        begin
        begin
                if reset = '1' then  -- reset counter
                if reset = '1' then  -- reset counter
                        steps_counter := 0;
                        steps_counter := 0;
                        overflow <= '0';
                        overflow <= '0';

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