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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [fifo_primitive.vhd] - Diff between revs 2 and 3

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------------------------------------------------------------------------------------ 
----------------------------------------------------------------------  
--                      
----  fifo_primitive                                              ---- 
-- Geoffrey Ottoy - DraMCo research group
----                                                              ---- 
--
----  This file is part of the                                    ----
-- Module Name: adder_n.vhd / entity adder_n
----    Modular Simultaneous Exponentiation Core project          ---- 
-- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
-- Last Modified:       04/04/2012 
----                                                              ---- 
-- 
----  Description                                                 ---- 
-- Description:         512x32-bit fifo
----    512 x 32 bit fifo                                         ----
--
----                                                              ---- 
--
----  Dependencies:                                               ----
-- Dependencies:        FIFO18E1 primitive
----    - FIFO18E1 (xilinx primitive)                             ----
--
----                                                              ----
-- Revision:
----  Authors:                                                    ----
--      Revision 1.00 - Architecture
----      - Geoffrey Ottoy, DraMCo research group                 ----
--      Revision 0.01 - File Created
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
--
----                                                              ---- 
--
---------------------------------------------------------------------- 
------------------------------------------------------------------------------------
----                                                              ---- 
--
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
-- NOTICE:
----                                                              ---- 
--
---- This source file may be used and distributed without         ---- 
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
---- restriction provided that this copyright statement is not    ---- 
-- by other third parties!
---- removed from the file and that any derivative work contains  ---- 
--
---- the original copyright notice and the associated disclaimer. ---- 
------------------------------------------------------------------------------------
----                                                              ---- 
library IEEE;
---- This source file is free software; you can redistribute it   ---- 
use IEEE.STD_LOGIC_1164.ALL;
---- and/or modify it under the terms of the GNU Lesser General   ---- 
use IEEE.STD_LOGIC_ARITH.ALL;
---- Public License as published by the Free Software Foundation; ---- 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- either version 2.1 of the License, or (at your option) any   ---- 
 
---- later version.                                               ---- 
 
----                                                              ---- 
 
---- This source is distributed in the hope that it will be       ---- 
 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
 
---- details.                                                     ---- 
 
----                                                              ---- 
 
---- You should have received a copy of the GNU Lesser General    ---- 
 
---- Public License along with this source; if not, download it   ---- 
 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
 
----                                                              ---- 
 
----------------------------------------------------------------------
 
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_unsigned.all;
 
 
---- Uncomment the following library declaration if instantiating
-- Xilinx primitives used in this code.
---- any Xilinx primitives in this code.
 
library UNISIM;
library UNISIM;
use UNISIM.VComponents.all;
use UNISIM.VComponents.all;
 
 
 
 
entity fifo_primitive is
entity fifo_primitive is
    Port ( clk : in  STD_LOGIC;
  port (
           din : in  STD_LOGIC_VECTOR (31 downto 0);
    clk    : in  std_logic;
           dout : out  STD_LOGIC_VECTOR (31 downto 0);
    din    : in  std_logic_vector (31 downto 0);
           empty : out  STD_LOGIC;
    dout   : out  std_logic_vector (31 downto 0);
           full : out  STD_LOGIC;
    empty  : out  std_logic;
           push : in  STD_LOGIC;
    full   : out  std_logic;
           pop : in  STD_LOGIC;
    push   : in  std_logic;
                          reset : in STD_LOGIC;
    pop    : in  std_logic;
                          nopop : out STD_LOGIC;
    reset  : in std_logic;
                          nopush : out STD_LOGIC
    nopop  : out std_logic;
 
    nopush : out std_logic
                          );
                          );
end fifo_primitive;
end fifo_primitive;
 
 
 
 
architecture Behavioral of fifo_primitive is
architecture Behavioral of fifo_primitive is
        signal rdcount : std_logic_vector(11 downto 0); -- debugging
        signal rdcount : std_logic_vector(11 downto 0); -- debugging
        signal wrcount : std_logic_vector(11 downto 0); -- debugging
        signal wrcount : std_logic_vector(11 downto 0); -- debugging
 
 
        signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
        signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
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      WREN => push_i                -- 1-bit write enable input
      WREN => push_i                -- 1-bit write enable input
   );
   );
 
 
end Behavioral;
end Behavioral;
 
 
 
 
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