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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Diff between revs 45 and 63

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use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
library mod_sim_exp;
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
use mod_sim_exp.std_functions.all;
 
 
-- toplevel of the modular simultaneous exponentiation core
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
-- and control logic
entity mod_sim_exp_core is
entity mod_sim_exp_core is
  generic(
  generic(
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true
    C_SPLIT_PIPELINE  : boolean := true;
 
    C_NR_OP           : integer := 4;
 
    C_NR_M            : integer := 2;
 
    C_FIFO_DEPTH      : integer := 32
  );
  );
  port(
  port(
    clk   : in  std_logic;
    clk   : in  std_logic;
    reset : in  std_logic;
    reset : in  std_logic;
      -- operand memory interface (plb shared memory)
      -- operand memory interface (plb shared memory)
    write_enable : in  std_logic; -- write data to operand ram
    write_enable : in  std_logic; -- write data to operand ram
    data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
    data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
    rw_address   : in  std_logic_vector (8 downto 0);   -- operand ram address bus
    rw_address   : in  std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0);   -- operand ram address bus
    data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
    data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
    collision    : out std_logic; -- write collision
    collision    : out std_logic; -- write collision
      -- op_sel fifo interface
      -- op_sel fifo interface
    fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
    fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
    fifo_push   : in  std_logic;  -- push data in exponent fifo
    fifo_push   : in  std_logic;  -- push data in exponent fifo
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    fifo_nopush : out std_logic;  -- high if error during push
    fifo_nopush : out std_logic;  -- high if error during push
      -- control signals
      -- control signals
    start          : in  std_logic; -- start multiplication/exponentiation
    start          : in  std_logic; -- start multiplication/exponentiation
    exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
    exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
    ready          : out std_logic; -- calculations done
    ready          : out std_logic; -- calculations done
    x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
    x_sel_single   : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
    y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
    y_sel_single   : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
    dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
    dest_op_single : in  std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
    p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
    p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
    calc_time      : out std_logic
    calc_time      : out std_logic;
 
    modulus_sel    : in std_logic_vector(log2(C_NR_M)-1 downto 0)
  );
  );
end mod_sim_exp_core;
end mod_sim_exp_core;
 
 
 
 
architecture Structural of mod_sim_exp_core is
architecture Structural of mod_sim_exp_core is
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    load_x   => load_x,
    load_x   => load_x,
    ready    => mult_ready
    ready    => mult_ready
  );
  );
 
 
  -- Block ram memory for storing the operands and the modulus
  -- Block ram memory for storing the operands and the modulus
  the_memory : operand_mem
  the_memory : operand_mem_gen
  generic map(
  generic map(
    n => C_NR_BITS_TOTAL
    width => C_NR_BITS_TOTAL,
 
    nr_op => C_NR_OP,
 
    nr_m  => C_NR_M
  )
  )
  port map(
  port map(
    data_in        => data_in,
    data_in        => data_in,
    data_out       => data_out,
    data_out       => data_out,
    rw_address     => rw_address,
    rw_address     => rw_address,
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    m              => m,
    m              => m,
    result_in      => r,
    result_in      => r,
    load_result    => load_result,
    load_result    => load_result,
    result_dest_op => result_dest_op,
    result_dest_op => result_dest_op,
    collision      => collision,
    collision      => collision,
    clk            => clk
    clk            => clk,
 
    modulus_sel     => modulus_sel
  );
  );
 
 
        result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
        result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
 
 
  -- A fifo for auto-run operand selection
  -- A fifo for auto-run operand selection
  the_exponent_fifo : fifo_primitive
  the_exponent_fifo : fifo_generic
 
  generic map(
 
    depth => C_FIFO_DEPTH
 
  )
  port map(
  port map(
    clk    => clk,
    clk    => clk,
    din    => fifo_din,
    din    => fifo_din,
    dout   => fifo_dout,
    dout   => fifo_dout,
    empty  => fifo_empty,
    empty  => fifo_empty,

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