Line 63... |
Line 63... |
generic(
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generic(
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_AW : integer := 7; -- Address width for FIFO pointers
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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clk : in std_logic;
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core_clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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bus_clk : in std_logic;
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write_enable : in std_logic; -- write data to operand ram
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write_enable : in std_logic; -- write data to operand ram
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
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rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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collision : out std_logic; -- write collision
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collision : out std_logic; -- write collision
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Line 113... |
Line 114... |
signal mult_ready : std_logic;
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signal mult_ready : std_logic;
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signal start_mult : std_logic;
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signal start_mult : std_logic;
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signal load_x : std_logic;
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signal load_x : std_logic;
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signal load_result : std_logic;
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signal load_result : std_logic;
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signal modulus_sel_i : std_logic_vector(0 downto 0);
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signal modulus_sel_i : std_logic_vector(0 downto 0);
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signal core_ready : std_logic;
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|
signal core_calc_time : std_logic;
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signal core_collision : std_logic;
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signal core_start : std_logic;
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|
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-- fifo signals
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-- fifo signals
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signal fifo_empty : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_nopop : std_logic;
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signal fifo_nopop : std_logic;
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Line 126... |
Line 131... |
assert (C_MEM_STYLE="xil_prim" or C_MEM_STYLE="generic" or C_MEM_STYLE="asym")
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assert (C_MEM_STYLE="xil_prim" or C_MEM_STYLE="generic" or C_MEM_STYLE="asym")
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report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure;
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report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure;
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assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera")
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assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera")
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report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure;
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report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure;
|
|
|
-- The actual multiplier
|
|
the_multiplier : mont_multiplier
|
|
generic map(
|
|
n => C_NR_BITS_TOTAL,
|
|
t => C_NR_STAGES_TOTAL,
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tl => C_NR_STAGES_LOW,
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|
split => C_SPLIT_PIPELINE
|
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)
|
|
port map(
|
|
core_clk => clk,
|
|
xy => xy,
|
|
m => m,
|
|
r => r,
|
|
start => start_mult,
|
|
reset => reset,
|
|
p_sel => p_sel,
|
|
load_x => load_x,
|
|
ready => mult_ready
|
|
);
|
|
|
|
-- Block ram memory for storing the operands and the modulus
|
-- Block ram memory for storing the operands and the modulus
|
the_memory : operand_mem
|
the_memory : operand_mem
|
generic map(
|
generic map(
|
width => C_NR_BITS_TOTAL,
|
width => C_NR_BITS_TOTAL,
|
nr_op => nr_op,
|
nr_op => nr_op,
|
nr_m => nr_m,
|
nr_m => nr_m,
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mem_style => C_MEM_STYLE,
|
mem_style => C_MEM_STYLE,
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device => C_FPGA_MAN
|
device => C_FPGA_MAN
|
)
|
)
|
port map(
|
port map(
|
|
bus_clk => bus_clk,
|
data_in => data_in,
|
data_in => data_in,
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data_out => data_out,
|
data_out => data_out,
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rw_address => rw_address,
|
rw_address => rw_address,
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write_enable => write_enable,
|
write_enable => write_enable,
|
op_sel => op_sel,
|
op_sel => op_sel,
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xy_out => xy,
|
xy_out => xy,
|
m => m,
|
m => m,
|
|
core_clk => core_clk,
|
result_in => r,
|
result_in => r,
|
load_result => load_result,
|
load_result => load_result,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
collision => collision,
|
collision => core_collision,
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clk => clk,
|
|
modulus_sel => modulus_sel_i
|
modulus_sel => modulus_sel_i
|
);
|
);
|
|
|
modulus_sel_i(0) <= modulus_sel;
|
modulus_sel_i(0) <= modulus_sel;
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
|
|
-- A fifo for exponentiation mode
|
-- A fifo for exponentiation mode
|
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
|
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
|
the_exponent_fifo : fifo_primitive
|
the_exponent_fifo : fifo_primitive
|
port map(
|
port map(
|
clk => clk,
|
push_clk => bus_clk,
|
|
pop_clk => core_clk,
|
din => fifo_din,
|
din => fifo_din,
|
dout => fifo_dout,
|
dout => fifo_dout,
|
empty => fifo_empty,
|
empty => fifo_empty,
|
full => fifo_full,
|
full => fifo_full,
|
push => fifo_push,
|
push => fifo_push,
|
Line 191... |
Line 178... |
nopop => fifo_nopop,
|
nopop => fifo_nopop,
|
nopush => fifo_nopush
|
nopush => fifo_nopush
|
);
|
);
|
end generate;
|
end generate;
|
gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate
|
gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate
|
the_exponent_fifo : fifo_generic
|
the_exponent_fifo : entity mod_sim_exp.generic_fifo_dc
|
generic map(
|
generic map(
|
depth => C_FIFO_DEPTH
|
dw => 32,
|
|
aw => C_FIFO_AW
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
wr_clk => bus_clk,
|
|
rd_clk => core_clk,
|
din => fifo_din,
|
din => fifo_din,
|
dout => fifo_dout,
|
dout => fifo_dout,
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empty => fifo_empty,
|
empty => fifo_empty,
|
full => fifo_full,
|
full => fifo_full,
|
push => fifo_push,
|
we => fifo_push,
|
pop => fifo_pop,
|
re => fifo_pop,
|
reset => reset,
|
clr => reset,
|
nopop => fifo_nopop,
|
nopop => fifo_nopop,
|
nopush => fifo_nopush
|
nopush => fifo_nopush
|
);
|
);
|
end generate;
|
end generate;
|
|
|
|
-- The actual multiplier
|
|
the_multiplier : mont_multiplier
|
|
generic map(
|
|
n => C_NR_BITS_TOTAL,
|
|
t => C_NR_STAGES_TOTAL,
|
|
tl => C_NR_STAGES_LOW,
|
|
split => C_SPLIT_PIPELINE
|
|
)
|
|
port map(
|
|
core_clk => core_clk,
|
|
xy => xy,
|
|
m => m,
|
|
r => r,
|
|
start => start_mult,
|
|
reset => reset, -- asynchronious reset
|
|
p_sel => p_sel,
|
|
load_x => load_x,
|
|
ready => mult_ready
|
|
);
|
|
|
-- The control logic for the core
|
-- The control logic for the core
|
the_control_unit : mont_ctrl
|
the_control_unit : mont_ctrl
|
port map(
|
port map(
|
clk => clk,
|
clk => core_clk,
|
reset => reset,
|
reset => reset, -- asynchronious reset
|
start => start,
|
start => core_start,
|
x_sel_single => x_sel_single,
|
x_sel_single => x_sel_single,
|
y_sel_single => y_sel_single,
|
y_sel_single => y_sel_single,
|
run_auto => exp_m,
|
run_auto => exp_m,
|
op_buffer_empty => fifo_empty,
|
op_buffer_empty => fifo_empty,
|
op_sel_buffer => fifo_dout,
|
op_sel_buffer => fifo_dout,
|
read_buffer => fifo_pop,
|
read_buffer => fifo_pop,
|
done => ready,
|
done => core_ready,
|
calc_time => calc_time,
|
calc_time => core_calc_time,
|
op_sel => op_sel,
|
op_sel => op_sel,
|
load_x => load_x,
|
load_x => load_x,
|
load_result => load_result,
|
load_result => load_result,
|
start_multiplier => start_mult,
|
start_multiplier => start_mult,
|
multiplier_ready => mult_ready
|
multiplier_ready => mult_ready
|
);
|
);
|
|
|
|
-- go from bus clock domain to core clock domain
|
|
start_pulse : pulse_cdc
|
|
port map(
|
|
reset => reset,
|
|
clkA => bus_clk,
|
|
pulseA => start,
|
|
clkB => core_clk,
|
|
pulseB => core_start
|
|
);
|
|
|
|
-- go from core clock domain to bus clock domain
|
|
ready_pulse : pulse_cdc
|
|
port map(
|
|
reset => reset,
|
|
clkA => core_clk,
|
|
pulseA => core_ready,
|
|
clkB => bus_clk,
|
|
pulseB => ready
|
|
);
|
|
|
|
sync_to_bus_clk : clk_sync
|
|
port map(
|
|
sigA => core_calc_time,
|
|
clkB => bus_clk,
|
|
sigB => calc_time
|
|
);
|
|
|
|
collision_pulse : pulse_cdc
|
|
port map(
|
|
reset => reset,
|
|
clkA => core_clk,
|
|
pulseA => core_collision,
|
|
clkB => bus_clk,
|
|
pulseB => collision
|
|
);
|
|
|
end Structural;
|
end Structural;
|
|
|
No newline at end of file
|
No newline at end of file
|