| Line 379... |
Line 379... |
start_first_stage : out std_logic; -- start pulse output for first stage
|
start_first_stage : out std_logic; -- start pulse output for first stage
|
stepping_done : out std_logic -- done signal
|
stepping_done : out std_logic -- done signal
|
);
|
);
|
end component stepping_logic;
|
end component stepping_logic;
|
|
|
|
--------------------------------------------------------------------
|
|
-- x_shift_reg
|
|
--------------------------------------------------------------------
|
|
-- shift register for the x operand of the multiplier
|
|
-- outputs the lsb of the register or bit at offset according to the
|
|
-- selected pipeline part
|
|
--
|
|
component x_shift_reg is
|
|
generic(
|
|
n : integer := 1536; -- width of the operands (# bits)
|
|
t : integer := 48; -- total number of stages
|
|
tl : integer := 16 -- lower number of stages
|
|
);
|
|
port(
|
|
-- clock input
|
|
clk : in std_logic;
|
|
-- x operand in (n-bit)
|
|
x_in : in std_logic_vector((n-1) downto 0);
|
|
-- control signals
|
|
reset : in std_logic; -- reset, clears register
|
|
load_x : in std_logic; -- load operand into shift register
|
|
next_x : in std_logic; -- next bit of x
|
|
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
|
|
-- x operand bit out (serial)
|
|
x_i : out std_logic
|
|
);
|
|
end component x_shift_reg;
|
|
|
component autorun_cntrl is
|
component autorun_cntrl is
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
start : in std_logic;
|
start : in std_logic;
|
| Line 586... |
Line 614... |
next_x : out std_logic;
|
next_x : out std_logic;
|
r : out std_logic_vector((n+1) downto 0)
|
r : out std_logic_vector((n+1) downto 0)
|
);
|
);
|
end component systolic_pipeline;
|
end component systolic_pipeline;
|
|
|
component x_shift_reg is
|
|
generic(
|
|
n : integer := 1536;
|
|
t : integer := 48;
|
|
tl : integer := 16
|
|
);
|
|
port(
|
|
clk : in std_logic;
|
|
reset : in std_logic;
|
|
x_in : in std_logic_vector((n-1) downto 0);
|
|
load_x : in std_logic;
|
|
next_x : in std_logic;
|
|
p_sel : in std_logic_vector(1 downto 0);
|
|
x_i : out std_logic
|
|
);
|
|
end component x_shift_reg;
|
|
|
|
end package mod_sim_exp_pkg;
|
end package mod_sim_exp_pkg;
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No newline at end of file
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|
