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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 41 and 43

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use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
 
 
package mod_sim_exp_pkg is
package mod_sim_exp_pkg is
  --------------------------------------------------------------------
  --------------------------------------------------------------------
  ------------------------- CORE PARAMETERS --------------------------
 
  --------------------------------------------------------------------
 
  -- These 4 parameters affect core workings
 
  constant nr_bits_total    : integer := 1536;
 
  constant nr_stages_total  : integer := 96;
 
  constant nr_stages_low    : integer := 32;
 
  constant split_pipeline   : boolean := true;
 
 
 
  -- extra calculated parameters
 
  constant nr_bits_low      : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
 
  constant nr_bits_high     : integer := nr_bits_total-nr_bits_low;
 
  constant nr_stages_high   : integer := nr_stages_total-nr_stages_low;
 
 
 
 
 
  --------------------------------------------------------------------
 
  ---------------------- COMPONENT DECLARATIONS ----------------------
  ---------------------- COMPONENT DECLARATIONS ----------------------
  --------------------------------------------------------------------
  --------------------------------------------------------------------
 
 
  --------------------------------------------------------------------
  --------------------------------------------------------------------
  -- d_flip_flop
  -- d_flip_flop
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  --    toplevel of the modular simultaneous exponentiation core
  --    toplevel of the modular simultaneous exponentiation core
  --    contains an operand and modulus ram, multiplier, an exponent fifo
  --    contains an operand and modulus ram, multiplier, an exponent fifo
  --    and control logic
  --    and control logic
  -- 
  -- 
  component mod_sim_exp_core is
  component mod_sim_exp_core is
 
    generic(
 
      C_NR_BITS_TOTAL : integer := 1536;
 
      C_NR_STAGES_TOTAL : integer := 96;
 
      C_NR_STAGES_LOW : integer := 32;
 
      C_SPLIT_PIPELINE : boolean := true
 
    );
    port(
    port(
      clk   : in  std_logic;
      clk   : in  std_logic;
      reset : in  std_logic;
      reset : in  std_logic;
        -- operand memory interface (plb shared memory)
        -- operand memory interface (plb shared memory)
      write_enable : in  std_logic; -- write data to operand ram
      write_enable : in  std_logic; -- write data to operand ram

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