| Line 896... |
Line 896... |
-- system clock
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-- system clock
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clk : in std_logic;
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clk : in std_logic;
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-- data interface (plb side)
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-- data interface (plb side)
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data_in : in std_logic_vector(31 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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write_enable : in std_logic;
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write_enable : in std_logic;
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-- operand interface (multiplier side)
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-- operand interface (multiplier side)
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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| Line 928... |
Line 928... |
generic(
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generic(
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_NR_OP : integer := 4;
|
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C_NR_M : integer := 2;
|
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable : in std_logic; -- write data to operand ram
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write_enable : in std_logic; -- write data to operand ram
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus
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rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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collision : out std_logic; -- write collision
|
collision : out std_logic; -- write collision
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-- op_sel fifo interface
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-- op_sel fifo interface
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fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
|
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
|
fifo_push : in std_logic; -- push data in exponent fifo
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fifo_push : in std_logic; -- push data in exponent fifo
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| Line 952... |
Line 950... |
fifo_nopush : out std_logic; -- high if error during push
|
fifo_nopush : out std_logic; -- high if error during push
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-- control signals
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-- control signals
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start : in std_logic; -- start multiplication/exponentiation
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start : in std_logic; -- start multiplication/exponentiation
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exp_m : in std_logic; -- single multiplication if low, exponentiation if high
|
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
|
ready : out std_logic; -- calculations done
|
ready : out std_logic; -- calculations done
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x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
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x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
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y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
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y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
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dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
|
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
|
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
|
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
|
calc_time : out std_logic;
|
calc_time : out std_logic;
|
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications
|
modulus_sel : in std_logic -- selects which modulus to use for multiplications
|
);
|
);
|
end component mod_sim_exp_core;
|
end component mod_sim_exp_core;
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|
|
|
|
end package mod_sim_exp_pkg;
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end package mod_sim_exp_pkg;
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