| Line 477... |
Line 477... |
port (
|
port (
|
clka : in std_logic;
|
clka : in std_logic;
|
wea : in std_logic_vector(0 downto 0);
|
wea : in std_logic_vector(0 downto 0);
|
addra : in std_logic_vector(5 downto 0);
|
addra : in std_logic_vector(5 downto 0);
|
dina : in std_logic_vector(31 downto 0);
|
dina : in std_logic_vector(31 downto 0);
|
douta : out std_logic_vector(511 downto 0);
|
douta : out std_logic_vector(31 downto 0);
|
clkb : in std_logic;
|
clkb : in std_logic;
|
web : in std_logic_vector(0 downto 0);
|
web : in std_logic_vector(0 downto 0);
|
addrb : in std_logic_vector(5 downto 0);
|
addrb : in std_logic_vector(1 downto 0);
|
dinb : in std_logic_vector(511 downto 0);
|
dinb : in std_logic_vector(511 downto 0);
|
doutb : out std_logic_vector(31 downto 0)
|
doutb : out std_logic_vector(511 downto 0)
|
);
|
);
|
end component operand_dp;
|
end component operand_dp;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- operand_sp
|
-- operand_sp
|
| Line 508... |
Line 508... |
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- a xilinx fifo primitive wrapper
|
-- a xilinx fifo primitive wrapper
|
--
|
--
|
component fifo_primitive is
|
component fifo_primitive is
|
port (
|
port (
|
clk : in std_logic;
|
pop_clk : in std_logic;
|
|
push_clk : in std_logic;
|
din : in std_logic_vector (31 downto 0);
|
din : in std_logic_vector (31 downto 0);
|
dout : out std_logic_vector (31 downto 0);
|
dout : out std_logic_vector (31 downto 0);
|
empty : out std_logic;
|
empty : out std_logic;
|
full : out std_logic;
|
full : out std_logic;
|
push : in std_logic;
|
push : in std_logic;
|
| Line 530... |
Line 531... |
-- uses xilinx primitives
|
-- uses xilinx primitives
|
--
|
--
|
component operand_ram is
|
component operand_ram is
|
port(
|
port(
|
-- global ports
|
-- global ports
|
clk : in std_logic;
|
|
collision : out std_logic;
|
collision : out std_logic;
|
-- bus side connections (32-bit serial)
|
-- bus side connections (32-bit serial)
|
|
bus_clk : in std_logic;
|
operand_addr : in std_logic_vector(5 downto 0);
|
operand_addr : in std_logic_vector(5 downto 0);
|
operand_in : in std_logic_vector(31 downto 0);
|
operand_in : in std_logic_vector(31 downto 0);
|
operand_in_sel : in std_logic_vector(1 downto 0);
|
operand_in_sel : in std_logic_vector(1 downto 0);
|
result_out : out std_logic_vector(31 downto 0);
|
result_out : out std_logic_vector(31 downto 0);
|
write_operand : in std_logic;
|
write_operand : in std_logic;
|
-- multiplier side connections (1536 bit parallel)
|
-- multiplier side connections (1536 bit parallel)
|
|
core_clk : in std_logic;
|
result_dest_op : in std_logic_vector(1 downto 0);
|
result_dest_op : in std_logic_vector(1 downto 0);
|
operand_out : out std_logic_vector(1535 downto 0);
|
operand_out : out std_logic_vector(1535 downto 0);
|
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
|
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
|
write_result : in std_logic;
|
write_result : in std_logic;
|
result_in : in std_logic_vector(1535 downto 0)
|
result_in : in std_logic_vector(1535 downto 0)
|
| Line 576... |
Line 578... |
component dpram_generic is
|
component dpram_generic is
|
generic (
|
generic (
|
depth : integer := 2
|
depth : integer := 2
|
);
|
);
|
port (
|
port (
|
clk : in std_logic;
|
-- write port A
|
-- write port
|
clkA : in std_logic;
|
waddr : in std_logic_vector(log2(depth)-1 downto 0);
|
waddrA : in std_logic_vector(log2(depth)-1 downto 0);
|
we : in std_logic;
|
weA : in std_logic;
|
din : in std_logic_vector(31 downto 0);
|
dinA : in std_logic_vector(31 downto 0);
|
-- read port
|
-- read port B
|
raddr : in std_logic_vector(log2(depth)-1 downto 0);
|
clkB : in std_logic;
|
dout : out std_logic_vector(31 downto 0)
|
raddrB : in std_logic_vector(log2(depth)-1 downto 0);
|
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
end component dpram_generic;
|
end component dpram_generic;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- tdpram_generic
|
-- tdpram_generic
|
| Line 649... |
Line 652... |
generic(
|
generic(
|
width : integer := 1536; -- must be a multiple of 32
|
width : integer := 1536; -- must be a multiple of 32
|
depth : integer := 2 -- nr of moduluses
|
depth : integer := 2 -- nr of moduluses
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
|
-- bus side
|
-- bus side
|
|
bus_clk : in std_logic;
|
write_modulus : in std_logic; -- write enable
|
write_modulus : in std_logic; -- write enable
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
-- multiplier side
|
-- multiplier side
|
|
core_clk : in std_logic;
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
);
|
);
|
end component modulus_ram_gen;
|
end component modulus_ram_gen;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
| Line 674... |
Line 678... |
width : integer := 1536; -- width of the operands
|
width : integer := 1536; -- width of the operands
|
depth : integer := 4 -- nr of operands
|
depth : integer := 4 -- nr of operands
|
);
|
);
|
port(
|
port(
|
-- global ports
|
-- global ports
|
clk : in std_logic;
|
|
collision : out std_logic; -- 1 if simultaneous write on RAM
|
collision : out std_logic; -- 1 if simultaneous write on RAM
|
-- bus side connections (32-bit serial)
|
-- bus side connections (32-bit serial)
|
|
bus_clk : in std_logic;
|
write_operand : in std_logic; -- write_enable
|
write_operand : in std_logic; -- write_enable
|
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
|
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
|
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
|
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
|
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
|
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
|
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
|
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
|
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
|
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
|
-- multiplier side connections (width-bit parallel)
|
-- multiplier side connections (width-bit parallel)
|
|
core_clk : in std_logic;
|
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
|
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
|
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
|
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
|
write_result : in std_logic; -- write enable for multiplier side
|
write_result : in std_logic; -- write enable for multiplier side
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
);
|
);
|
| Line 710... |
Line 715... |
rddepth : integer := 4; -- nr of 32-bit words
|
rddepth : integer := 4; -- nr of 32-bit words
|
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
|
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
|
device : string := "xilinx" -- device template to use
|
device : string := "xilinx" -- device template to use
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
|
-- write port
|
-- write port
|
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
|
clkA : in std_logic;
|
we : in std_logic;
|
waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
|
din : in std_logic_vector(wrwidth-1 downto 0);
|
weA : in std_logic;
|
|
dinA : in std_logic_vector(wrwidth-1 downto 0);
|
-- read port
|
-- read port
|
raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
|
clkB : in std_logic;
|
dout : out std_logic_vector(31 downto 0)
|
raddrB : in std_logic_vector(log2(rddepth)-1 downto 0);
|
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
end component dpram_asym;
|
end component dpram_asym;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- dpramblock_asym
|
-- dpramblock_asym
|
| Line 735... |
Line 741... |
width : integer := 256; -- read width
|
width : integer := 256; -- read width
|
depth : integer := 2; -- nr of (width)-bit words
|
depth : integer := 2; -- nr of (width)-bit words
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
-- write port A
|
-- write port
|
clkA : in std_logic;
|
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
we : in std_logic;
|
weA : in std_logic;
|
din : in std_logic_vector(31 downto 0);
|
dinA : in std_logic_vector(31 downto 0);
|
-- read port
|
-- read port B
|
raddr : in std_logic_vector(log2(depth)-1 downto 0);
|
clkB : in std_logic;
|
dout : out std_logic_vector(width-1 downto 0)
|
raddrB : in std_logic_vector(log2(depth)-1 downto 0);
|
|
doutB : out std_logic_vector(width-1 downto 0)
|
);
|
);
|
end component dpramblock_asym;
|
end component dpramblock_asym;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- tdpram_asym
|
-- tdpram_asym
|
| Line 761... |
Line 768... |
depthB : integer := 4; -- nr of 32-bit words
|
depthB : integer := 4; -- nr of 32-bit words
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
|
-- port A (widthA)-bit
|
-- port A (widthA)-bit
|
|
clkA : in std_logic;
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
weA : in std_logic;
|
weA : in std_logic;
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
-- port B 32-bit
|
-- port B 32-bit
|
|
clkB : in std_logic;
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
weB : in std_logic;
|
weB : in std_logic;
|
dinB : in std_logic_vector(31 downto 0);
|
dinB : in std_logic_vector(31 downto 0);
|
doutB : out std_logic_vector(31 downto 0)
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
| Line 789... |
Line 797... |
depth : integer := 4; -- nr of (width)-bit words
|
depth : integer := 4; -- nr of (width)-bit words
|
width : integer := 512; -- width of portB
|
width : integer := 512; -- width of portB
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port (
|
port (
|
clk : in std_logic;
|
|
-- port A 32-bit
|
-- port A 32-bit
|
|
clkA : in std_logic;
|
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
weA : in std_logic;
|
weA : in std_logic;
|
dinA : in std_logic_vector(31 downto 0);
|
dinA : in std_logic_vector(31 downto 0);
|
doutA : out std_logic_vector(31 downto 0);
|
doutA : out std_logic_vector(31 downto 0);
|
-- port B (width)-bit
|
-- port B (width)-bit
|
|
clkB : in std_logic;
|
addrB : in std_logic_vector(log2(depth)-1 downto 0);
|
addrB : in std_logic_vector(log2(depth)-1 downto 0);
|
weB : in std_logic;
|
weB : in std_logic;
|
dinB : in std_logic_vector(width-1 downto 0);
|
dinB : in std_logic_vector(width-1 downto 0);
|
doutB : out std_logic_vector(width-1 downto 0)
|
doutB : out std_logic_vector(width-1 downto 0)
|
);
|
);
|
| Line 820... |
Line 829... |
width : integer := 1536; -- must be a multiple of 32
|
width : integer := 1536; -- must be a multiple of 32
|
depth : integer := 2; -- nr of moduluses
|
depth : integer := 2; -- nr of moduluses
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
|
-- bus side
|
-- bus side
|
|
bus_clk : in std_logic;
|
write_modulus : in std_logic; -- write enable
|
write_modulus : in std_logic; -- write enable
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
-- multiplier side
|
-- multiplier side
|
|
core_clk : in std_logic;
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
);
|
);
|
end component modulus_ram_asym;
|
end component modulus_ram_asym;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
| Line 850... |
Line 860... |
depth : integer := 4; -- nr of operands
|
depth : integer := 4; -- nr of operands
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port(
|
port(
|
-- global ports
|
-- global ports
|
clk : in std_logic;
|
|
collision : out std_logic; -- 1 if simultaneous write on RAM
|
collision : out std_logic; -- 1 if simultaneous write on RAM
|
-- bus side connections (32-bit serial)
|
-- bus side connections (32-bit serial)
|
|
bus_clk : in std_logic;
|
write_operand : in std_logic; -- write_enable
|
write_operand : in std_logic; -- write_enable
|
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
|
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
|
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
|
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
|
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
|
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
|
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
|
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
|
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
|
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
|
-- multiplier side connections (width-bit parallel)
|
-- multiplier side connections (width-bit parallel)
|
|
core_clk : in std_logic;
|
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
|
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
|
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
|
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
|
write_result : in std_logic; -- write enable for multiplier side
|
write_result : in std_logic; -- write enable for multiplier side
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
);
|
);
|
| Line 891... |
Line 902... |
nr_m : integer := 2; -- nr of modulus storages
|
nr_m : integer := 2; -- nr of modulus storages
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
device : string := "altera" -- xilinx, altera are valid options
|
device : string := "altera" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
-- system clock
|
|
clk : in std_logic;
|
|
-- data interface (plb side)
|
-- data interface (plb side)
|
|
bus_clk : in std_logic;
|
data_in : in std_logic_vector(31 downto 0);
|
data_in : in std_logic_vector(31 downto 0);
|
data_out : out std_logic_vector(31 downto 0);
|
data_out : out std_logic_vector(31 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
write_enable : in std_logic;
|
write_enable : in std_logic;
|
-- operand interface (multiplier side)
|
-- operand interface (multiplier side)
|
|
core_clk : in std_logic;
|
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
|
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
|
xy_out : out std_logic_vector((width-1) downto 0);
|
xy_out : out std_logic_vector((width-1) downto 0);
|
m : out std_logic_vector((width-1) downto 0);
|
m : out std_logic_vector((width-1) downto 0);
|
result_in : in std_logic_vector((width-1) downto 0);
|
result_in : in std_logic_vector((width-1) downto 0);
|
-- control signals
|
-- control signals
|
| Line 911... |
Line 922... |
collision : out std_logic;
|
collision : out std_logic;
|
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
|
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
|
);
|
);
|
end component operand_mem;
|
end component operand_mem;
|
|
|
|
---------------------- CLOCK DOMAIN CROSSING ----------------------
|
|
|
|
component pulse_cdc is
|
|
port (
|
|
reset : in std_logic;
|
|
clkA : in std_logic;
|
|
pulseA : in std_logic;
|
|
clkB : in std_logic;
|
|
pulseB : out std_logic
|
|
);
|
|
end component pulse_cdc;
|
|
|
|
component clk_sync is
|
|
port (
|
|
sigA : in std_logic;
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clkB : in std_logic;
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sigB : out std_logic
|
|
);
|
|
end component clk_sync;
|
|
|
---------------------------- TOP LEVEL -----------------------------
|
---------------------------- TOP LEVEL -----------------------------
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- mod_sim_exp_core
|
-- mod_sim_exp_core
|
| Line 929... |
Line 958... |
C_NR_BITS_TOTAL : integer := 1536;
|
C_NR_BITS_TOTAL : integer := 1536;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_FIFO_DEPTH : integer := 32;
|
C_FIFO_DEPTH : integer := 32;
|
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
|
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
|
C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
core_clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
|
bus_clk : in std_logic;
|
write_enable : in std_logic; -- write data to operand ram
|
write_enable : in std_logic; -- write data to operand ram
|
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
|
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
|
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
|
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
|
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
|
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
|
collision : out std_logic; -- write collision
|
collision : out std_logic; -- write collision
|
