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----------------------------------------------------------------------------------
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----------------------------------------------------------------------
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-- Company:
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---- modulus_ram ----
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-- Engineer:
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---- ----
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--
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---- This file is part of the ----
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-- Create Date: 13:57:21 03/08/2012
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---- Modular Simultaneous Exponentiation Core project ----
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-- Design Name:
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Module Name: modulus_ram - Behavioral
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---- ----
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-- Project Name:
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---- Description ----
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-- Target Devices:
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---- BRAM memory and logic to store the 1536-bit modulus ----
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-- Tool versions:
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---- ----
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-- Description:
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---- Dependencies: ----
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--
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---- - operands_sp (coregen) ----
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-- Dependencies:
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---- ----
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--
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---- Authors: ----
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-- Revision:
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 0.01 - File Created
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---- - Jonas De Craene, JonasDC@opencores.org ----
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-- Additional Comments:
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---- ----
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------------------
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---- ----
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library IEEE;
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- This source file may be used and distributed without ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- Uncomment the following library declaration if instantiating
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---- the original copyright notice and the associated disclaimer. ----
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---- any Xilinx primitives in this code.
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---- ----
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--library UNISIM;
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---- This source file is free software; you can redistribute it ----
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--use UNISIM.VComponents.all;
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity modulus_ram is
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entity modulus_ram is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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modulus_addr : in std_logic_vector(5 downto 0);
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modulus_addr : in std_logic_vector(5 downto 0);
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modulus_in : in std_logic_vector(31 downto 0);
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modulus_in : in std_logic_vector(31 downto 0);
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modulus_out : out std_logic_vector(1535 downto 0)
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modulus_out : out std_logic_vector(1535 downto 0)
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);
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);
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end modulus_ram;
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end modulus_ram;
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architecture Behavioral of modulus_ram is
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-- single port blockram to store modulus
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component operands_sp
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port(
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clka: in std_logic;
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wea: in std_logic_vector(0 downto 0);
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addra: in std_logic_vector(4 downto 0);
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dina: in std_logic_vector(31 downto 0);
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douta: out std_logic_vector(511 downto 0)
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);
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end component;
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architecture Behavioral of modulus_ram is
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signal part_enable : std_logic_vector(3 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal addra : std_logic_vector(4 downto 0);
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signal addra : std_logic_vector(4 downto 0);
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begin
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begin
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addra => addra,
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addra => addra,
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dina => modulus_in,
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dina => modulus_in,
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douta => modulus_out(1535 downto 1024)
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douta => modulus_out(1535 downto 1024)
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);
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);
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-- modulus_3 : operands_sp
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-- port map (
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-- clka => clk,
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-- wea => wea(3 downto 3),
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-- addra => addra,
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-- dina => modulus_in,
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-- douta => modulus_out(2047 downto 1536)
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-- );
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end Behavioral;
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end Behavioral;
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