Line 62... |
Line 62... |
--
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--
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entity modulus_ram_asym is
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entity modulus_ram_asym is
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generic(
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generic(
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width : integer := 1536; -- must be a multiple of 32
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width : integer := 1536; -- must be a multiple of 32
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depth : integer := 2; -- nr of moduluses
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depth : integer := 2; -- nr of moduluses
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device : string := "altera"
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device : string := "xilinx"
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);
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);
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port(
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port(
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clk : in std_logic;
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-- bus side
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-- bus side
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bus_clk : in std_logic;
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write_modulus : in std_logic; -- write enable
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write_modulus : in std_logic; -- write enable
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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-- multiplier side
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-- multiplier side
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core_clk : in std_logic;
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modulus_out : out std_logic_vector(width-1 downto 0)
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modulus_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end modulus_ram_asym;
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end modulus_ram_asym;
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architecture structural of modulus_ram_asym is
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architecture structural of modulus_ram_asym is
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Line 106... |
Line 105... |
width => width,
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width => width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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-- write port
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-- write port
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clkA => bus_clk,
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waddr => waddr,
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waddrA => waddr,
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we => write_modulus,
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weA => write_modulus,
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din => modulus_in,
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dinA => modulus_in,
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-- read port
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-- read port
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clkB => core_clk,
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raddr => modulus_sel,
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raddrB => modulus_sel,
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dout => modulus_out
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doutB => modulus_out
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);
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);
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end generate;
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end generate;
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multiple_full_blocks : if (width > RAMblock_maxwidth) generate
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multiple_full_blocks : if (width > RAMblock_maxwidth) generate
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-- signals for multiple blocks
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-- signals for multiple blocks
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Line 135... |
Line 133... |
width => RAMblock_maxwidth,
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width => RAMblock_maxwidth,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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-- write port
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-- write port
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clkA => bus_clk,
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waddr => waddr,
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waddrA => waddr,
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we => we_RAM(i),
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weA => we_RAM(i),
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din => modulus_in,
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dinA => modulus_in,
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-- read port
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-- read port
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clkB => core_clk,
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raddr => modulus_sel,
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raddrB => modulus_sel,
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dout => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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doutB => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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);
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);
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-- we
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-- we
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process (write_modulus, modulus_addr)
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process (write_modulus, modulus_addr)
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begin
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begin
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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Line 170... |
Line 167... |
width => RAMblock_part_width,
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width => RAMblock_part_width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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-- write port
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-- write port
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clkA => bus_clk,
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waddr => waddr_part,
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waddrA => waddr_part,
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we => we_part,
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weA => we_part,
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din => modulus_in,
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dinA => modulus_in,
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-- read port
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-- read port
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clkB => core_clk,
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raddr => modulus_sel,
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raddrB => modulus_sel,
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dout => modulus_out(width-1 downto i*RAMblock_maxwidth)
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doutB => modulus_out(width-1 downto i*RAMblock_maxwidth)
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);
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);
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-- we_part
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-- we_part
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process (write_modulus, modulus_addr)
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process (write_modulus, modulus_addr)
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begin
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begin
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