OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_asym.vhd] - Diff between revs 90 and 94

Show entire file | Details | Blame | View Log

Rev 90 Rev 94
Line 62... Line 62...
--
--
entity modulus_ram_asym is
entity modulus_ram_asym is
  generic(
  generic(
    width : integer := 1536;  -- must be a multiple of 32
    width : integer := 1536;  -- must be a multiple of 32
    depth : integer := 2;     -- nr of moduluses
    depth : integer := 2;     -- nr of moduluses
    device : string := "xilinx"
    device : string := "altera"
  );
  );
  port(
  port(
    clk            : in std_logic;
 
      -- bus side
      -- bus side
 
    bus_clk        : in std_logic;
    write_modulus  : in std_logic; -- write enable
    write_modulus  : in std_logic; -- write enable
    modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
    modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
    modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
    modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
    modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
    modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
    modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
    modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
      -- multiplier side
      -- multiplier side
 
    core_clk       : in std_logic;
    modulus_out    : out std_logic_vector(width-1 downto 0)
    modulus_out    : out std_logic_vector(width-1 downto 0)
  );
  );
end modulus_ram_asym;
end modulus_ram_asym;
 
 
architecture structural of modulus_ram_asym is
architecture structural of modulus_ram_asym is
Line 105... Line 106...
      width => width,
      width => width,
      depth => depth,
      depth => depth,
      device  => device
      device  => device
    )
    )
    port map(
    port map(
      clk => clk,
 
      -- write port
      -- write port
      waddr => waddr,
      clkA   => bus_clk,
      we    => write_modulus,
      waddrA => waddr,
      din   => modulus_in,
      weA    => write_modulus,
 
      dinA   => modulus_in,
      -- read port
      -- read port
      raddr => modulus_sel,
      clkB   => core_clk,
      dout  => modulus_out
      raddrB => modulus_sel,
 
      doutB  => modulus_out
    );
    );
  end generate;
  end generate;
 
 
  multiple_full_blocks : if (width > RAMblock_maxwidth) generate
  multiple_full_blocks : if (width > RAMblock_maxwidth) generate
    -- signals for multiple blocks
    -- signals for multiple blocks
Line 133... Line 135...
          width  => RAMblock_maxwidth,
          width  => RAMblock_maxwidth,
          depth  => depth,
          depth  => depth,
          device => device
          device => device
        )
        )
        port map(
        port map(
          clk => clk,
 
          -- write port
          -- write port
          waddr => waddr,
          clkA   => bus_clk,
          we    => we_RAM(i),
          waddrA => waddr,
          din   => modulus_in,
          weA    => we_RAM(i),
 
          dinA   => modulus_in,
          -- read port
          -- read port
          raddr => modulus_sel,
          clkB   => core_clk,
          dout  => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
          raddrB => modulus_sel,
 
          doutB  => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
        );
        );
        -- we
        -- we
        process (write_modulus, modulus_addr)
        process (write_modulus, modulus_addr)
        begin
        begin
          if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
          if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
Line 167... Line 170...
          width  => RAMblock_part_width,
          width  => RAMblock_part_width,
          depth  => depth,
          depth  => depth,
          device => device
          device => device
        )
        )
        port map(
        port map(
          clk => clk,
 
          -- write port
          -- write port
          waddr => waddr_part,
          clkA   => bus_clk,
          we    => we_part,
          waddrA => waddr_part,
          din   => modulus_in,
          weA    => we_part,
 
          dinA   => modulus_in,
          -- read port
          -- read port
          raddr => modulus_sel,
          clkB   => core_clk,
          dout  => modulus_out(width-1 downto i*RAMblock_maxwidth)
          raddrB => modulus_sel,
 
          doutB  => modulus_out(width-1 downto i*RAMblock_maxwidth)
        );
        );
 
 
        -- we_part
        -- we_part
        process (write_modulus, modulus_addr)
        process (write_modulus, modulus_addr)
        begin
        begin

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.