| Line 59... |
Line 59... |
generic(
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generic(
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width : integer := 1536; -- must be a multiple of 32
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width : integer := 1536; -- must be a multiple of 32
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depth : integer := 2 -- nr of moduluses
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depth : integer := 2 -- nr of moduluses
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);
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);
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port(
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port(
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clk : in std_logic;
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|
-- bus side
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-- bus side
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bus_clk : in std_logic;
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write_modulus : in std_logic; -- write enable
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write_modulus : in std_logic; -- write enable
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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-- multiplier side
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-- multiplier side
|
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core_clk : in std_logic;
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modulus_out : out std_logic_vector(width-1 downto 0)
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modulus_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end modulus_ram_gen;
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end modulus_ram_gen;
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|
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architecture Behavioral of modulus_ram_gen is
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architecture Behavioral of modulus_ram_gen is
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| Line 94... |
Line 95... |
ramblock: dpram_generic
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ramblock: dpram_generic
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generic map(
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generic map(
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depth => depth
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depth => depth
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)
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)
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port map(
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port map(
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clk => clk,
|
|
-- write port
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-- write port
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waddr => modulus_wraddr(total_aw-1 downto RAMselect_aw),
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clkA => bus_clk,
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we => we(i),
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waddrA => modulus_wraddr(total_aw-1 downto RAMselect_aw),
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din => modulus_in,
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weA => we(i),
|
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dinA => modulus_in,
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-- read port
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-- read port
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raddr => modulus_rdaddr,
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clkB => core_clk,
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dout => modulus_out(((i+1)*32)-1 downto i*32)
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raddrB => modulus_rdaddr,
|
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doutB => modulus_out(((i+1)*32)-1 downto i*32)
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);
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);
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-- connect the w
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-- connect the w
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process (write_modulus, modulus_wraddr)
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process (write_modulus, modulus_wraddr)
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begin
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begin
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if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
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if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
|
