| Line 59... |
Line 59... |
generic(
|
generic(
|
width : integer := 1536; -- must be a multiple of 32
|
width : integer := 1536; -- must be a multiple of 32
|
depth : integer := 2 -- nr of moduluses
|
depth : integer := 2 -- nr of moduluses
|
);
|
);
|
port(
|
port(
|
|
clk : in std_logic;
|
-- bus side
|
-- bus side
|
bus_clk : in std_logic;
|
|
write_modulus : in std_logic; -- write enable
|
write_modulus : in std_logic; -- write enable
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
-- multiplier side
|
-- multiplier side
|
core_clk : in std_logic;
|
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
);
|
);
|
end modulus_ram_gen;
|
end modulus_ram_gen;
|
|
|
architecture Behavioral of modulus_ram_gen is
|
architecture Behavioral of modulus_ram_gen is
|
| Line 95... |
Line 94... |
ramblock: dpram_generic
|
ramblock: dpram_generic
|
generic map(
|
generic map(
|
depth => depth
|
depth => depth
|
)
|
)
|
port map(
|
port map(
|
|
clk => clk,
|
-- write port
|
-- write port
|
clkA => bus_clk,
|
waddr => modulus_wraddr(total_aw-1 downto RAMselect_aw),
|
waddrA => modulus_wraddr(total_aw-1 downto RAMselect_aw),
|
we => we(i),
|
weA => we(i),
|
din => modulus_in,
|
dinA => modulus_in,
|
|
-- read port
|
-- read port
|
clkB => core_clk,
|
raddr => modulus_rdaddr,
|
raddrB => modulus_rdaddr,
|
dout => modulus_out(((i+1)*32)-1 downto i*32)
|
doutB => modulus_out(((i+1)*32)-1 downto i*32)
|
|
);
|
);
|
-- connect the w
|
-- connect the w
|
process (write_modulus, modulus_wraddr)
|
process (write_modulus, modulus_wraddr)
|
begin
|
begin
|
if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
|
if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
|
