| Line 70... |
Line 70... |
generic(
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generic(
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width : integer := 1536; -- width of the operands
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width : integer := 1536; -- width of the operands
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
nr_m : integer := 2; -- nr of modulus storages
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nr_m : integer := 2; -- nr of modulus storages
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mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
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mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
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device : string := "xilinx" -- xilinx, altera are valid options
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device : string := "altera" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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-- system clock
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clk : in std_logic;
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-- data interface (plb side)
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-- data interface (plb side)
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bus_clk : in std_logic;
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data_in : in std_logic_vector(31 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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write_enable : in std_logic;
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write_enable : in std_logic;
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-- operand interface (multiplier side)
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-- operand interface (multiplier side)
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core_clk : in std_logic;
|
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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result_in : in std_logic_vector((width-1) downto 0);
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result_in : in std_logic_vector((width-1) downto 0);
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-- control signals
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-- control signals
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| Line 130... |
Line 130... |
|
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xil_prim_RAM : if mem_style="xil_prim" generate
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xil_prim_RAM : if mem_style="xil_prim" generate
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-- xy operand storage
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-- xy operand storage
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xy_ram_xil : operand_ram
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xy_ram_xil : operand_ram
|
port map(
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port map(
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bus_clk => bus_clk,
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clk => clk,
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core_clk => core_clk,
|
|
collision => collision,
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collision => collision,
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operand_addr => xy_addr_i,
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operand_addr => xy_addr_i,
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operand_in => xy_data_i,
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operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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operand_in_sel => operand_in_sel_i,
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result_out => data_out,
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result_out => data_out,
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| Line 148... |
Line 147... |
);
|
);
|
|
|
-- modulus storage
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-- modulus storage
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m_ram_xil : modulus_ram
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m_ram_xil : modulus_ram
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port map(
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port map(
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clk => bus_clk,
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clk => clk,
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modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
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write_modulus => load_m,
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write_modulus => load_m,
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modulus_in => m_data_i,
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modulus_in => m_data_i,
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modulus_out => m
|
modulus_out => m
|
);
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);
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| Line 164... |
Line 163... |
generic map(
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generic map(
|
width => width,
|
width => width,
|
depth => nr_op
|
depth => nr_op
|
)
|
)
|
port map(
|
port map(
|
|
clk => clk,
|
collision => collision,
|
collision => collision,
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bus_clk => bus_clk,
|
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
write_operand => load_op,
|
write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
core_clk => core_clk,
|
|
write_result => load_result,
|
write_result => load_result,
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result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
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| Line 186... |
Line 184... |
generic map(
|
generic map(
|
width => width,
|
width => width,
|
depth => nr_m
|
depth => nr_m
|
)
|
)
|
port map(
|
port map(
|
bus_clk => bus_clk,
|
clk => clk,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
core_clk => core_clk,
|
|
modulus_out => m,
|
modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 206... |
Line 203... |
width => width,
|
width => width,
|
depth => nr_op,
|
depth => nr_op,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
|
clk => clk,
|
collision => collision,
|
collision => collision,
|
bus_clk => bus_clk,
|
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
write_operand => load_op,
|
write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
core_clk => core_clk,
|
|
write_result => load_result,
|
write_result => load_result,
|
result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
| Line 229... |
Line 225... |
width => width,
|
width => width,
|
depth => nr_m,
|
depth => nr_m,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
bus_clk => bus_clk,
|
clk => clk,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
core_clk => core_clk,
|
|
modulus_out => m,
|
modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
end generate;
|
end generate;
|
|
|
