----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- operand_mem ----
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---- operand_mem ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- RAM memory and logic to the store operands and the ----
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---- RAM memory and logic to the store operands and the ----
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---- modulus for the montgomery multiplier, the user has a ----
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---- modulus for the montgomery multiplier, the user has a ----
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---- choise between 3 memory styles, more detail in the ----
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---- choise between 3 memory styles, more detail in the ----
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---- documentation ----
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---- documentation ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - operand_ram ----
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---- - operand_ram ----
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---- - modulus_ram ----
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---- - modulus_ram ----
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---- - operand_ram_gen ----
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---- - operand_ram_gen ----
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---- - modulus_ram_gen ----
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---- - modulus_ram_gen ----
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---- - operand_ram_asym ----
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---- - operand_ram_asym ----
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---- - modulus_ram_asym ----
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---- - modulus_ram_asym ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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|
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-- address structure:
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-- address structure:
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-- bit: 8 -> '1': modulus
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-- bit: 8 -> '1': modulus
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-- '0': operands
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-- '0': operands
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-- bits: 7-6 -> operand_in_sel in case of highest bit = '0'
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-- bits: 7-6 -> operand_in_sel in case of highest bit = '0'
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-- modulus_in_sel in case of highest bit = '1'
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-- modulus_in_sel in case of highest bit = '1'
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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--
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--
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entity operand_mem is
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entity operand_mem is
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generic(
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generic(
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width : integer := 1536; -- width of the operands
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width : integer := 1536; -- width of the operands
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
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nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
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nr_m : integer := 2; -- nr of modulus storages
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nr_m : integer := 2; -- nr of modulus storages
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mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
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mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
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device : string := "altera" -- xilinx, altera are valid options
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device : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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-- system clock
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clk : in std_logic;
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-- data interface (plb side)
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-- data interface (plb side)
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bus_clk : in std_logic;
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data_in : in std_logic_vector(31 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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write_enable : in std_logic;
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write_enable : in std_logic;
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-- operand interface (multiplier side)
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-- operand interface (multiplier side)
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core_clk : in std_logic;
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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result_in : in std_logic_vector((width-1) downto 0);
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result_in : in std_logic_vector((width-1) downto 0);
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-- control signals
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-- control signals
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load_result : in std_logic;
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load_result : in std_logic;
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result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
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result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
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collision : out std_logic;
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collision : out std_logic;
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modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
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modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
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);
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);
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end operand_mem;
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end operand_mem;
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|
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architecture structural of operand_mem is
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architecture structural of operand_mem is
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-- constants
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-- constants
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constant wordaddr_aw : integer := log2(width/32);
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constant wordaddr_aw : integer := log2(width/32);
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constant opaddr_aw : integer := log2(nr_op);
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constant opaddr_aw : integer := log2(nr_op);
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constant maddr_aw : integer := log2(nr_m);
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constant maddr_aw : integer := log2(nr_m);
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constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
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constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
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|
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-- internal signals
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-- internal signals
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
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signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
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signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
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signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
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|
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signal load_op : std_logic;
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signal load_op : std_logic;
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|
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signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
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signal load_m : std_logic;
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signal load_m : std_logic;
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signal m_data_i : std_logic_vector(31 downto 0);
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signal m_data_i : std_logic_vector(31 downto 0);
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|
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begin
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begin
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|
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-- map inputs
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-- map inputs
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xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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operand_in_sel_i <= rw_address(7 downto 6);
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operand_in_sel_i <= rw_address(7 downto 6);
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modulus_in_sel_i <= rw_address(6 downto 6);
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modulus_in_sel_i <= rw_address(6 downto 6);
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xy_data_i <= data_in;
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xy_data_i <= data_in;
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m_data_i <= data_in;
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m_data_i <= data_in;
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-- select right memory with highest address bit
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-- select right memory with highest address bit
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load_op <= write_enable when (rw_address(8) = '0') else '0';
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load_op <= write_enable when (rw_address(8) = '0') else '0';
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load_m <= write_enable when (rw_address(8) = '1') else '0';
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load_m <= write_enable when (rw_address(8) = '1') else '0';
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|
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xil_prim_RAM : if mem_style="xil_prim" generate
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xil_prim_RAM : if mem_style="xil_prim" generate
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-- xy operand storage
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-- xy operand storage
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xy_ram_xil : operand_ram
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xy_ram_xil : operand_ram
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port map(
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port map(
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clk => clk,
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bus_clk => bus_clk,
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core_clk => core_clk,
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collision => collision,
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collision => collision,
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operand_addr => xy_addr_i,
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operand_addr => xy_addr_i,
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operand_in => xy_data_i,
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operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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operand_in_sel => operand_in_sel_i,
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result_out => data_out,
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result_out => data_out,
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write_operand => load_op,
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write_operand => load_op,
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operand_out => xy_out,
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operand_out => xy_out,
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operand_out_sel => op_sel,
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operand_out_sel => op_sel,
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result_dest_op => result_dest_op,
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result_dest_op => result_dest_op,
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write_result => load_result,
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write_result => load_result,
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result_in => result_in
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result_in => result_in
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);
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);
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|
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-- modulus storage
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-- modulus storage
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m_ram_xil : modulus_ram
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m_ram_xil : modulus_ram
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port map(
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port map(
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clk => clk,
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clk => bus_clk,
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modulus_addr => m_addr_i,
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modulus_addr => m_addr_i,
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write_modulus => load_m,
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write_modulus => load_m,
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modulus_in => m_data_i,
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modulus_in => m_data_i,
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modulus_out => m
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modulus_out => m
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);
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);
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end generate;
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end generate;
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gen_RAM : if mem_style="generic" generate
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gen_RAM : if mem_style="generic" generate
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-- xy operand storage
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-- xy operand storage
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xy_ram_gen : operand_ram_gen
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xy_ram_gen : operand_ram_gen
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generic map(
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generic map(
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width => width,
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width => width,
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depth => nr_op
|
depth => nr_op
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
|
collision => collision,
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collision => collision,
|
|
bus_clk => bus_clk,
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
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operand_in => xy_data_i,
|
operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
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result_out => data_out,
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write_operand => load_op,
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write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
|
core_clk => core_clk,
|
write_result => load_result,
|
write_result => load_result,
|
result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
m_ram_gen : modulus_ram_gen
|
m_ram_gen : modulus_ram_gen
|
generic map(
|
generic map(
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width => width,
|
width => width,
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depth => nr_m
|
depth => nr_m
|
)
|
)
|
port map(
|
port map(
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clk => clk,
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bus_clk => bus_clk,
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modulus_in_sel => modulus_in_sel_i,
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modulus_in_sel => modulus_in_sel_i,
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modulus_addr => m_addr_i,
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modulus_addr => m_addr_i,
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write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
|
core_clk => core_clk,
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modulus_out => m,
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modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
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end generate;
|
end generate;
|
|
|
asym_RAM : if mem_style="asym" generate
|
asym_RAM : if mem_style="asym" generate
|
-- xy operand storage
|
-- xy operand storage
|
xy_ram_asym : operand_ram_asym
|
xy_ram_asym : operand_ram_asym
|
generic map(
|
generic map(
|
width => width,
|
width => width,
|
depth => nr_op,
|
depth => nr_op,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
|
collision => collision,
|
collision => collision,
|
|
bus_clk => bus_clk,
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
write_operand => load_op,
|
write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
|
core_clk => core_clk,
|
write_result => load_result,
|
write_result => load_result,
|
result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
m_ram_asym : modulus_ram_asym
|
m_ram_asym : modulus_ram_asym
|
generic map(
|
generic map(
|
width => width,
|
width => width,
|
depth => nr_m,
|
depth => nr_m,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
bus_clk => bus_clk,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
|
core_clk => core_clk,
|
modulus_out => m,
|
modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
end generate;
|
end generate;
|
|
|
end structural;
|
end structural;
|
|
|