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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
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Rev 39 |
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Line 84... |
signal addrb : std_logic_vector(5 downto 0);
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signal addrb : std_logic_vector(5 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal doutb0 : std_logic_vector(31 downto 0);
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signal doutb0 : std_logic_vector(31 downto 0);
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signal doutb1 : std_logic_vector(31 downto 0);
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signal doutb1 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal doutb3 : std_logic_vector(31 downto 0);
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begin
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begin
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-- WARNING: Very Important!
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-- WARNING: Very Important!
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-- wea & web signals must never be high at the same time !!
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-- wea & web signals must never be high at the same time !!
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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result_out <= doutb0 when "00",
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result_out <= doutb0 when "00",
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doutb1 when "01",
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doutb1 when "01",
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doutb2 when "10",
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doutb2 when others;
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doutb3 when others;
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-- 3 instances of a dual port ram to store the parts of the operand
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-- 3 instances of a dual port ram to store the parts of the operand
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op_0 : operand_dp
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op_0 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => clk,
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