Subversion Repositories mod_sim_exp

  signal addrb  : std_logic_vector(5 downto 0);

  signal addrb  : std_logic_vector(5 downto 0);

  signal web    : std_logic_vector(0 downto 0);

  signal web    : std_logic_vector(0 downto 0);

  signal doutb0 : std_logic_vector(31 downto 0);

  signal doutb0 : std_logic_vector(31 downto 0);

  signal doutb1 : std_logic_vector(31 downto 0);

  signal doutb1 : std_logic_vector(31 downto 0);

  signal doutb2 : std_logic_vector(31 downto 0);

  signal doutb2 : std_logic_vector(31 downto 0);

begin

begin

        -- WARNING: Very Important!

        -- WARNING: Very Important!

        -- wea & web signals must never be high at the same time !!

        -- wea & web signals must never be high at the same time !!

        with operand_addr(5 downto 4) select

        with operand_addr(5 downto 4) select

                result_out <= doutb0 when "00",

                result_out <= doutb0 when "00",

                              doutb1 when "01",

                              doutb1 when "01",

        -- 3 instances of a dual port ram to store the parts of the operand

        -- 3 instances of a dual port ram to store the parts of the operand

  op_0 : operand_dp

  op_0 : operand_dp

  port map (

  port map (

    clka  => clk,

    clka  => clk,