OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Diff between revs 69 and 81

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 69 Rev 81
Line 51... Line 51...
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
library mod_sim_exp;
library mod_sim_exp;
 
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.std_functions.all;
use mod_sim_exp.std_functions.all;
 
 
-- structural description of a RAM to hold the operands, with 
-- structural description of a RAM to hold the operands, with 
-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
--    formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number) 
--    formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number) 
Line 116... Line 117...
  single_block : if (width <= RAMblock_maxwidth) generate
  single_block : if (width <= RAMblock_maxwidth) generate
    -- signals for single block
    -- signals for single block
    signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
    signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
  begin
  begin
    addrA_single <= operand_in_sel & operand_addr;
    addrA_single <= operand_in_sel & operand_addr;
    ramblock : entity mod_sim_exp.tdpramblock_asym
    ramblock : tdpramblock_asym
    generic map(
    generic map(
      depth  => depth,
      depth  => depth,
      width  => width,
      width  => width,
      device => device
      device => device
    )
    )
Line 149... Line 150...
    ramblocks_full : for i in 0 to nrRAMblocks_full generate
    ramblocks_full : for i in 0 to nrRAMblocks_full generate
      -- port A signals
      -- port A signals
      addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
      addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
 
 
      full_ones : if (i < nrRAMblocks_full) generate
      full_ones : if (i < nrRAMblocks_full) generate
        ramblock_full : entity mod_sim_exp.tdpramblock_asym
        ramblock_full : tdpramblock_asym
        generic map(
        generic map(
          depth  => depth,
          depth  => depth,
          width  => RAMblock_maxwidth,
          width  => RAMblock_maxwidth,
          device => device
          device => device
        )
        )
Line 198... Line 199...
        -- signals for part
        -- signals for part
        signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
        signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
        signal weA_part   : std_logic;
        signal weA_part   : std_logic;
      begin
      begin
        addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
        addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
        ramblock_part : entity mod_sim_exp.tdpramblock_asym
        ramblock_part : tdpramblock_asym
        generic map(
        generic map(
          depth  => depth,
          depth  => depth,
          width  => RAMblock_part_width,
          width  => RAMblock_part_width,
          device => device
          device => device
        )
        )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.