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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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-- structural description of a RAM to hold the operands, with
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-- structural description of a RAM to hold the operands, with
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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single_block : if (width <= RAMblock_maxwidth) generate
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single_block : if (width <= RAMblock_maxwidth) generate
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-- signals for single block
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-- signals for single block
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signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
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signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
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begin
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begin
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addrA_single <= operand_in_sel & operand_addr;
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addrA_single <= operand_in_sel & operand_addr;
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ramblock : entity mod_sim_exp.tdpramblock_asym
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ramblock : tdpramblock_asym
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generic map(
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generic map(
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depth => depth,
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depth => depth,
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width => width,
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width => width,
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device => device
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device => device
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)
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)
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ramblocks_full : for i in 0 to nrRAMblocks_full generate
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ramblocks_full : for i in 0 to nrRAMblocks_full generate
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-- port A signals
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-- port A signals
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addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
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addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
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full_ones : if (i < nrRAMblocks_full) generate
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full_ones : if (i < nrRAMblocks_full) generate
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ramblock_full : entity mod_sim_exp.tdpramblock_asym
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ramblock_full : tdpramblock_asym
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generic map(
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generic map(
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depth => depth,
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depth => depth,
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width => RAMblock_maxwidth,
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width => RAMblock_maxwidth,
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device => device
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device => device
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)
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)
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-- signals for part
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-- signals for part
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signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal weA_part : std_logic;
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signal weA_part : std_logic;
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begin
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begin
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addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
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addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
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ramblock_part : entity mod_sim_exp.tdpramblock_asym
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ramblock_part : tdpramblock_asym
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generic map(
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generic map(
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depth => depth,
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depth => depth,
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width => RAMblock_part_width,
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width => RAMblock_part_width,
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device => device
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device => device
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)
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)
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