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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Diff between revs 90 and 94

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Rev 90 Rev 94
Line 66... Line 66...
    depth  : integer := 4;    -- nr of operands
    depth  : integer := 4;    -- nr of operands
    device : string  := "xilinx"
    device : string  := "xilinx"
  );
  );
  port(
  port(
      -- global ports
      -- global ports
    clk       : in std_logic;
 
    collision : out std_logic; -- 1 if simultaneous write on RAM
    collision : out std_logic; -- 1 if simultaneous write on RAM
      -- bus side connections (32-bit serial)
      -- bus side connections (32-bit serial)
 
    bus_clk        : in std_logic;
    write_operand  : in std_logic; -- write_enable
    write_operand  : in std_logic; -- write_enable
    operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
    operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
    operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
    operand_addr   : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
    operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
    operand_in     : in std_logic_vector(31 downto 0);  -- operand word(32-bit) to write
    result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
    result_out     : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
    operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
    operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
      -- multiplier side connections (width-bit parallel)
      -- multiplier side connections (width-bit parallel)
 
    core_clk        : in std_logic;
    result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
    result_dest_op  : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
    operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
    operand_out     : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
    write_result    : in std_logic; -- write enable for multiplier side
    write_result    : in std_logic; -- write enable for multiplier side
    result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
    result_in       : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
  );
  );
Line 124... Line 125...
      depth  => depth,
      depth  => depth,
      width  => width,
      width  => width,
      device => device
      device => device
    )
    )
    port map(
    port map(
      clk => clk,
 
      -- port A 32-bit
      -- port A 32-bit
 
      clkA  => bus_clk,
      addrA => addrA_single,
      addrA => addrA_single,
      weA   => write_operand_i,
      weA   => write_operand_i,
      dinA  => operand_in,
      dinA  => operand_in,
      doutA => result_out,
      doutA => result_out,
      -- port B (width)-bit
      -- port B (width)-bit
 
      clkB  => core_clk,
      addrB => mult_op_sel,
      addrB => mult_op_sel,
      weB   => write_result,
      weB   => write_result,
      dinB  => result_in,
      dinB  => result_in,
      doutB => operand_out
      doutB => operand_out
    );
    );
Line 157... Line 159...
          depth  => depth,
          depth  => depth,
          width  => RAMblock_maxwidth,
          width  => RAMblock_maxwidth,
          device => device
          device => device
        )
        )
        port map(
        port map(
          clk => clk,
 
          -- port A 32-bit
          -- port A 32-bit
 
          clkA  => bus_clk,
          addrA => addrA,
          addrA => addrA,
          weA   => weA_RAM(i),
          weA   => weA_RAM(i),
          dinA  => operand_in,
          dinA  => operand_in,
          doutA => doutA_RAM(i),
          doutA => doutA_RAM(i),
          -- port B (width)-bit
          -- port B (width)-bit
 
          clkB  => core_clk,
          addrB => mult_op_sel,
          addrB => mult_op_sel,
          weB   => write_result,
          weB   => write_result,
          dinB  => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
          dinB  => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
          doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
          doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
        );
        );
Line 206... Line 209...
          depth  => depth,
          depth  => depth,
          width  => RAMblock_part_width,
          width  => RAMblock_part_width,
          device => device
          device => device
        )
        )
        port map(
        port map(
          clk => clk,
 
          -- port A 32-bit
          -- port A 32-bit
 
          clkA  => bus_clk,
          addrA => addrA_part,
          addrA => addrA_part,
          weA   => weA_part,
          weA   => weA_part,
          dinA  => operand_in,
          dinA  => operand_in,
          doutA => doutA_RAM(i),
          doutA => doutA_RAM(i),
          -- port B (width)-bit
          -- port B (width)-bit
 
          clkB  => core_clk,
          addrB => mult_op_sel,
          addrB => mult_op_sel,
          weB   => write_result,
          weB   => write_result,
          dinB  => result_in(width-1 downto i*RAMblock_maxwidth),
          dinB  => result_in(width-1 downto i*RAMblock_maxwidth),
          doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
          doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
        );
        );

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