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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_1b.vhd] - Diff between revs 3 and 6

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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    1 bit register                                            ----
----    1 bit register with active high asynchronious reset and ce----
----    used in montgommery multiplier systolic array stages      ----            
----    used in montgommery multiplier systolic array stages      ----            
----                                                              ---- 
----                                                              ---- 
----  Dependencies: none                                          ----
----  Dependencies: none                                          ----
----                                                              ----
----                                                              ----
----  Authors:                                                    ----
----  Authors:                                                    ----
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
-- Xilinx primitives used
-- 1-bit register with asynchronous reset and clock enable
library UNISIM;
 
use UNISIM.VComponents.all;
 
 
 
 
 
entity register_1b is
entity register_1b is
  port(
  port(
    core_clk : in  std_logic;
    core_clk : in  std_logic; -- clock input
    ce       : in  std_logic;
    ce       : in  std_logic; -- clock enable (active high)
    reset    : in  std_logic;
    reset    : in  std_logic; -- reset (active high)
    din      : in  std_logic;
    din      : in  std_logic; -- data in
    dout     : out std_logic
    dout     : out std_logic  -- data out
  );
  );
end register_1b;
end register_1b;
 
 
 
 
architecture Structural of register_1b is
architecture Behavorial of register_1b is
        signal dout_i : std_logic;
 
begin
begin
 
 
        dout <= dout_i;
        -- process for 1-bit register
 
  reg_1b : process (reset, ce, core_clk, din)
 
  begin
 
    if reset='1' then -- asynchronous active high reset
 
      dout <= '0';
 
    else
 
      if rising_edge(core_clk) then -- clock in data on rising edge
 
        if ce='1' then  -- active high clock enable to clock in data
 
          dout <= din;
 
        end if;
 
      end if;
 
    end if;
 
  end process;
 
 
  FDCE_inst : FDCE
end Behavorial;
  generic map (
 
    INIT => '0'      -- Initial value of latch ('0' or '1')
 
  )
 
  port map (
 
    Q   => dout_i,   -- Data output
 
    CLR => reset,    -- Asynchronous clear/reset input
 
    D   => din,      -- Data input
 
    C   => core_clk, -- Gate input
 
    CE  => ce        -- Gate enable input
 
  );
 
 
 
end Structural;
 
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