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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- 1 bit register ----
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---- 1 bit register with active high asynchronious reset and ce----
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---- used in montgommery multiplier systolic array stages ----
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---- used in montgommery multiplier systolic array stages ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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-- Xilinx primitives used
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-- 1-bit register with asynchronous reset and clock enable
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library UNISIM;
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use UNISIM.VComponents.all;
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entity register_1b is
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entity register_1b is
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port(
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port(
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core_clk : in std_logic;
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core_clk : in std_logic; -- clock input
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ce : in std_logic;
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ce : in std_logic; -- clock enable (active high)
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reset : in std_logic;
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reset : in std_logic; -- reset (active high)
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din : in std_logic;
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din : in std_logic; -- data in
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dout : out std_logic
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dout : out std_logic -- data out
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);
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);
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end register_1b;
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end register_1b;
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architecture Structural of register_1b is
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architecture Behavorial of register_1b is
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signal dout_i : std_logic;
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begin
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begin
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dout <= dout_i;
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-- process for 1-bit register
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reg_1b : process (reset, ce, core_clk, din)
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begin
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if reset='1' then -- asynchronous active high reset
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dout <= '0';
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else
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if rising_edge(core_clk) then -- clock in data on rising edge
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if ce='1' then -- active high clock enable to clock in data
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dout <= din;
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end if;
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end if;
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end if;
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end process;
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FDCE_inst : FDCE
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end Behavorial;
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generic map (
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INIT => '0' -- Initial value of latch ('0' or '1')
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)
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port map (
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Q => dout_i, -- Data output
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CLR => reset, -- Asynchronous clear/reset input
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D => din, -- Data input
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C => core_clk, -- Gate input
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CE => ce -- Gate enable input
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);
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end Structural;
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No newline at end of file
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No newline at end of file
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