URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Diff between revs 7 and 15

Rev 7	Rev 15
Line 48...	Line 48...
`use ieee.std_logic_unsigned.all;`	`use ieee.std_logic_unsigned.all;`

`-- n-bit register with asynchronous reset and clock enable`	`-- n-bit register with asynchronous reset and clock enable`
`entity register_n is`	`entity register_n is`
`generic(`	`generic(`
`n : integer := 4`	`width : integer := 4`
`);`	`);`
`port(`	`port(`
`core_clk : in std_logic; -- clock input`	`core_clk : in std_logic; -- clock input`
`ce : in std_logic; -- clock enable (active high)`	`ce : in std_logic; -- clock enable (active high)`
`reset : in std_logic; -- reset (active high)`	`reset : in std_logic; -- reset (active high)`
`din : in std_logic_vector((n-1) downto 0); -- data in (n-bit)`	`din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit`
`dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit)`	`dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit`
`);`	`);`
`end register_n;`	`end register_n;`


`architecture Behavorial of register_n is`	`architecture Behavorial of register_n is`
`begin`	`begin`
`-- process for n-bit register`	`-- process for (width)-bit register`
`reg_nb : process (reset, ce, core_clk, din)`	`reg_nb : process (reset, ce, core_clk, din)`
`begin`	`begin`
`if reset='1' then -- asynchronous active high reset`	`if reset='1' then -- asynchronous active high reset`
`dout <= (others=>'0');`	`dout <= (others=>'0');`
`else`	`else`