| Line 1... |
Line 1... |
------------------------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
---- standard_cell_block ----
|
-- Geoffrey Ottoy - DraMCo research group
|
---- ----
|
--
|
---- This file is part of the ----
|
-- Module Name: standard_cell_block.vhd / entity standard_cell_block
|
---- Modular Simultaneous Exponentiation Core project ----
|
--
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
-- Last Modified: 14/11/2011
|
---- ----
|
--
|
---- Description ----
|
-- Description: cell_block for use in the montgommery multiplier systolic array
|
---- a block of [width] cell_1b cells for use in the ----
|
--
|
---- montgommery multiplier systolic array ----
|
--
|
---- ----
|
-- Dependencies: none
|
---- Dependencies: ----
|
--
|
---- - cell_1b ----
|
-- Revision:
|
---- ----
|
-- Revision 1.00 - Architecture
|
---- Authors: ----
|
-- Revision 0.01 - File Created
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
--
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
--
|
---- ----
|
------------------------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
---- ----
|
-- NOTICE:
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
--
|
---- ----
|
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
|
---- This source file may be used and distributed without ----
|
-- by other third parties!
|
---- restriction provided that this copyright statement is not ----
|
--
|
---- removed from the file and that any derivative work contains ----
|
------------------------------------------------------------------------------------
|
---- the original copyright notice and the associated disclaimer. ----
|
library IEEE;
|
---- ----
|
use IEEE.STD_LOGIC_1164.ALL;
|
---- This source file is free software; you can redistribute it ----
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
---- Public License as published by the Free Software Foundation; ----
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- Uncomment the following library declaration if instantiating
|
---- later version. ----
|
---- any Xilinx primitives in this code.
|
---- ----
|
--library UNISIM;
|
---- This source is distributed in the hope that it will be ----
|
--use UNISIM.VComponents.all;
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
|
---- details. ----
|
|
---- ----
|
|
---- You should have received a copy of the GNU Lesser General ----
|
|
---- Public License along with this source; if not, download it ----
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
|
---- ----
|
|
----------------------------------------------------------------------
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.std_logic_arith.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
library mod_sim_exp;
|
|
use mod_sim_exp.mod_sim_exp_pkg.all;
|
|
|
|
|
entity standard_cell_block is
|
entity standard_cell_block is
|
generic ( width : integer := 16
|
generic (
|
|
width : integer := 16
|
|
);
|
|
port (
|
|
my : in std_logic_vector((width-1) downto 0);
|
|
y : in std_logic_vector((width-1) downto 0);
|
|
m : in std_logic_vector((width-1) downto 0);
|
|
x : in std_logic;
|
|
q : in std_logic;
|
|
a : in std_logic_vector((width-1) downto 0);
|
|
cin : in std_logic;
|
|
cout : out std_logic;
|
|
r : out std_logic_vector((width-1) downto 0)
|
);
|
);
|
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
|
|
y : in STD_LOGIC_VECTOR((width-1) downto 0);
|
|
m : in STD_LOGIC_VECTOR((width-1) downto 0);
|
|
x : in STD_LOGIC;
|
|
q : in STD_LOGIC;
|
|
a : in STD_LOGIC_VECTOR((width-1) downto 0);
|
|
cin : in STD_LOGIC;
|
|
cout : out STD_LOGIC;
|
|
r : out STD_LOGIC_VECTOR((width-1) downto 0));
|
|
end standard_cell_block;
|
end standard_cell_block;
|
|
|
architecture Structural of standard_cell_block is
|
|
component cell_1b
|
|
Port ( my : in STD_LOGIC;
|
|
y : in STD_LOGIC;
|
|
m : in STD_LOGIC;
|
|
x : in STD_LOGIC;
|
|
q : in STD_LOGIC;
|
|
a : in STD_LOGIC;
|
|
cin : in STD_LOGIC;
|
|
cout : out STD_LOGIC;
|
|
r : out STD_LOGIC);
|
|
end component;
|
|
|
|
|
architecture Structural of standard_cell_block is
|
signal carry : std_logic_vector(width downto 0);
|
signal carry : std_logic_vector(width downto 0);
|
begin
|
begin
|
|
|
carry(0) <= cin;
|
carry(0) <= cin;
|
|
|
cell_block: for i in 0 to (width-1) generate
|
cell_block: for i in 0 to (width-1) generate
|
cells: cell_1b
|
cells: cell_1b
|
port map( my => my(i),
|
port map(
|
|
my => my(i),
|
y => y(i),
|
y => y(i),
|
m => m(i),
|
m => m(i),
|
x => x,
|
x => x,
|
q => q,
|
q => q,
|
a => a(i),
|
a => a(i),
|
| Line 80... |
Line 91... |
);
|
);
|
end generate;
|
end generate;
|
|
|
cout <= carry(width);
|
cout <= carry(width);
|
end Structural;
|
end Structural;
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
