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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- stepping logic for the pipelined montgomery multiplier ----
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---- stepping logic to control the pipeline for one ----
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---- montgommery multiplication ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - d_flip_flop ----
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---- - d_flip_flop ----
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---- - counter_sync ----
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---- - counter_sync ----
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---- ----
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---- ----
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- stepping logic for the pipeline, generates the start pulses for the
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-- first stage and keeps track of when the last stages are done
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entity stepping_logic is
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entity stepping_logic is
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generic(
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generic(
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n : integer := 1536; -- max nr of steps required to complete a multiplication
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n : integer := 1536; -- max nr of steps required to complete a multiplication
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t : integer := 192 -- total nr of steps in the pipeline
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t : integer := 192 -- total nr of steps in the pipeline
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);
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);
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port(
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port(
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core_clk : in std_logic;
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core_clk : in std_logic; -- clock input
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start : in std_logic;
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start : in std_logic; -- start signal for pipeline (one multiplication)
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reset : in std_logic;
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reset : in std_logic; -- reset signal
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t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
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t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
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n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
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n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
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start_first_stage : out std_logic;
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start_first_stage : out std_logic; -- start pulse output for first stage
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stepping_done : out std_logic
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stepping_done : out std_logic -- done signal
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);
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);
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end stepping_logic;
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end stepping_logic;
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architecture Behavioral of stepping_logic is
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architecture Behavioral of stepping_logic is
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signal laststeps_in_i : std_logic := '0';
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signal laststeps_out_i : std_logic := '0';
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-- signals for the first stage control, pulses and counters
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signal start_stop_in_i : std_logic := '0';
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signal first_stage_done : std_logic; -- indicates the first stage is done running for this multiplication
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signal start_stop_out_i : std_logic := '0';
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signal first_stage_active : std_logic; -- indicates the first stage is active
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signal steps_in_i : std_logic := '0';
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signal first_stage_active_d : std_logic; -- delayed version of first_stage_active
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signal steps_out_i : std_logic := '0';
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signal start_first_stage_i : std_logic; -- internal version of start_first_stage output
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signal substeps_in_i : std_logic := '0';
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signal substeps_out_i : std_logic := '0';
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-- signals for the last stages control and counter
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signal done_reg_in_i : std_logic := '0';
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signal last_stages_done : std_logic; -- indicates the last stages are done running for this multiplication
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signal done_reg_out_i : std_logic := '0';
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signal last_stages_active : std_logic; -- indicates the last stages are active
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signal start_first_stage_i : std_logic := '0';
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signal last_stages_active_d : std_logic; -- delayed version of last_stages_active
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signal start_i : std_logic := '0';
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begin
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begin
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start_i <= start;
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-- map outputs
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-- map outputs
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start_first_stage <= start_first_stage_i;
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stepping_done <= last_stages_done;
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stepping_done <= laststeps_out_i;
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-- internal signals
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-- internal signals
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start_stop_in_i <= start_i or (start_stop_out_i and not steps_out_i);
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--------------------
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substeps_in_i <= start_stop_in_i;
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-- first_stage_active signal gets active from a start pulse
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steps_in_i <= substeps_out_i;
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-- inactive from first_stage_done pulse
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done_reg_in_i <= steps_out_i or (done_reg_out_i and not laststeps_out_i);
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first_stage_active <= start or (first_stage_active_d and not first_stage_done);
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laststeps_in_i <= done_reg_in_i;
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start_first_stage_i <= start_i or steps_in_i;
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-- done signal gets active from a first_stage_done pulse
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--start_first_stage_i <= steps_in_i;
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-- inactive from last_stages_done pulse
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last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done);
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-- map start_first_stage_i to output, but also use the initial start pulse
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start_first_stage <= start or start_first_stage_i;
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done_reg : d_flip_flop
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last_stages_active_delay : d_flip_flop
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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reset => reset,
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reset => reset,
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din => done_reg_in_i,
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din => last_stages_active,
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dout => done_reg_out_i
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dout => last_stages_active_d
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);
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);
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start_stop_reg : d_flip_flop
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first_stage_active_delay : d_flip_flop
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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reset => reset,
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reset => reset,
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din => start_stop_in_i,
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din => first_stage_active,
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dout => start_stop_out_i
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dout => first_stage_active_d
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);
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);
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-- for counting the last steps
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-- the counters
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----------------
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-- for counting the last steps (waiting for the other stages to stop)
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-- counter for keeping track of how many stages are done
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laststeps_counter : counter_sync
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laststeps_counter : counter_sync
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generic map(
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generic map(
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max_value => t
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max_value => t
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)
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)
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port map(
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port map(
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reset_value => t_sel,
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reset_value => t_sel,
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core_clk => core_clk,
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core_clk => core_clk,
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ce => laststeps_in_i,
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ce => last_stages_active,
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reset => reset,
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reset => reset,
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overflow => laststeps_out_i
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overflow => last_stages_done
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);
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);
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-- counter for keeping track of the steps
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-- counter for keeping track of how many times the first stage is started
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-- counts bits in operand x till operand width then generates pulse on first_stage_done
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steps_counter : counter_sync
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steps_counter : counter_sync
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generic map(
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generic map(
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max_value => n
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max_value => n
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)
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)
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port map(
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port map(
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reset_value => (n_sel),
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reset_value => (n_sel),
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core_clk => core_clk,
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core_clk => core_clk,
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ce => steps_in_i,
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ce => start_first_stage_i,
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reset => reset,
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reset => reset,
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overflow => steps_out_i
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overflow => first_stage_done
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);
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);
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-- makes sure we don't start too early with a new step
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-- the output (overflow) of this counter starts the first stage every 2 clock cycles
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substeps_counter : counter_sync
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substeps_counter : counter_sync
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generic map(
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generic map(
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max_value => 2
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max_value => 2
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)
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)
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port map(
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port map(
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reset_value => 2,
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reset_value => 2,
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core_clk => core_clk,
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core_clk => core_clk,
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ce => substeps_in_i,
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ce => first_stage_active,
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reset => reset,
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reset => reset,
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overflow => substeps_out_i
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overflow => start_first_stage_i
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);
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);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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