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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [sys_last_cell_logic.vhd] - Diff between revs 30 and 39
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Rev 39 |
| Line 66... |
Line 66... |
);
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);
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end sys_last_cell_logic;
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end sys_last_cell_logic;
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architecture Behavorial of sys_last_cell_logic is
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architecture Behavorial of sys_last_cell_logic is
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signal cell_result_high : std_logic_vector(1 downto 0);
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signal cin_reg : std_logic;
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signal cell_result_high_reg : std_logic_vector(1 downto 0);
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signal red_cout_end : std_logic;
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begin
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begin
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-- half adder: cout_last_stage + cell_result_high_reg(1)
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a_0 <= cin_reg;
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cell_result_high(0) <= cin xor cell_result_high_reg(1); --result
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cell_result_high(1) <= cin and cell_result_high_reg(1); --cout
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last_reg : register_1b
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a_0 <= cell_result_high_reg(0);
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last_reg : register_n
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generic map(
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width => 2
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)
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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ce => start,
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ce => start,
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reset => reset,
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reset => reset,
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din => cell_result_high,
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din => cin,
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dout => cell_result_high_reg
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dout => cin_reg
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);
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);
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-- reduction, finishing last 2 bits
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-- reduction, finishing last bit
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reduction_adder_a : cell_1b_adder
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reduction_adder : cell_1b_adder
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port map(
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port map(
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a => '1', -- for 2s complement of m
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a => '1', -- for 2s complement of m
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b => cell_result_high_reg(0),
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b => cin_reg,
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cin => red_cin,
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cin => red_cin,
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cout => red_cout_end
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);
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reduction_adder_b : cell_1b_adder
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port map(
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a => '1', -- for 2s complement of m
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b => cell_result_high_reg(1),
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cin => red_cout_end,
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cout => r_sel
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cout => r_sel
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);
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);
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end Behavorial;
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end Behavorial;
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