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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [sys_pipeline.vhd] - Diff between revs 25 and 30

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Rev 25 Rev 30
Line 105... Line 105...
 
 
  -- first cell signals
  -- first cell signals
  signal my0_mux_result : std_logic;
  signal my0_mux_result : std_logic;
  signal my0 : std_logic;
  signal my0 : std_logic;
 
 
  -- last cell signals
 
  signal a_high : std_logic_vector(1 downto 0);
 
  signal a_high_reg : std_logic_vector(1 downto 0);
 
  signal red_cout_end : std_logic_vector(1 downto 0);
 
 
 
 
 
begin
begin
 
 
  m_i <= '0' & m;
  m_i <= '0' & m;
  y_i <= '0' & y;
  y_i <= '0' & y;
 
 
Line 182... Line 176...
 
 
  next_x <= done_stage(0);
  next_x <= done_stage(0);
 
 
  -- last cell logic
  -- last cell logic
  -------------------
  -------------------
  -- half adder: cout_stage(t-1) + a_high_reg(1)
  last_cell : sys_last_cell_logic
  a_high(0) <= cout_stage(t-1) xor a_high_reg(1); --result
 
  a_high(1) <= cout_stage(t-1) and a_high_reg(1); --cout
 
 
 
  a_msb_stage(t-1) <= a_high_reg(0);
 
 
 
  last_reg : register_n
 
  generic map(
 
    width => 2
 
  )
 
  port map(
  port map(
    core_clk => core_clk,
    core_clk => core_clk,
    ce       => done_stage(t-1),
 
    reset    => reset,
    reset    => reset,
    din      => a_high,
    a_0      => a_msb_stage(t-1),
    dout     => a_high_reg
    cin      => cout_stage(t-1),
  );
    red_cin  => red_cout_stage(t-1),
 
    r_sel    => r_sel,
  -- reduction finishing last 2 bits
    start    => done_stage(t-1)
  reduction_adder_a : cell_1b_adder
 
  port map(
 
    a     => '1', -- for 2s complement of m
 
    b     => a_high_reg(0),
 
    cin   => red_cout_stage(t-1),
 
    cout  => red_cout_end(0)
 
  );
 
 
 
  reduction_adder_b : cell_1b_adder
 
  port map(
 
    a     => '1', -- for 2s complement of m
 
    b     => a_high_reg(1),
 
    cin   => red_cout_end(0),
 
    cout  => red_cout_end(1)
 
  );
  );
 
 
  r_sel <= red_cout_end(1);
 
 
 
end Structural;
end Structural;
 
 
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