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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
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-- first cell signals
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-- first cell signals
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signal my0_mux_result : std_logic;
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signal my0_mux_result : std_logic;
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signal my0 : std_logic;
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signal my0 : std_logic;
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-- last cell signals
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signal a_high : std_logic_vector(1 downto 0);
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signal a_high_reg : std_logic_vector(1 downto 0);
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signal red_cout_end : std_logic_vector(1 downto 0);
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begin
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begin
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m_i <= '0' & m;
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m_i <= '0' & m;
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y_i <= '0' & y;
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y_i <= '0' & y;
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next_x <= done_stage(0);
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next_x <= done_stage(0);
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-- last cell logic
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-- last cell logic
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-------------------
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-------------------
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-- half adder: cout_stage(t-1) + a_high_reg(1)
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last_cell : sys_last_cell_logic
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a_high(0) <= cout_stage(t-1) xor a_high_reg(1); --result
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a_high(1) <= cout_stage(t-1) and a_high_reg(1); --cout
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a_msb_stage(t-1) <= a_high_reg(0);
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last_reg : register_n
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generic map(
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width => 2
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)
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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ce => done_stage(t-1),
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reset => reset,
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reset => reset,
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din => a_high,
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a_0 => a_msb_stage(t-1),
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dout => a_high_reg
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cin => cout_stage(t-1),
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);
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red_cin => red_cout_stage(t-1),
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r_sel => r_sel,
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-- reduction finishing last 2 bits
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start => done_stage(t-1)
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reduction_adder_a : cell_1b_adder
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port map(
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a => '1', -- for 2s complement of m
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b => a_high_reg(0),
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cin => red_cout_stage(t-1),
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cout => red_cout_end(0)
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);
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reduction_adder_b : cell_1b_adder
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port map(
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a => '1', -- for 2s complement of m
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b => a_high_reg(1),
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cin => red_cout_end(0),
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cout => red_cout_end(1)
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);
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);
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r_sel <= red_cout_end(1);
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end Structural;
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end Structural;
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