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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- 1536 bit shift register with lsb output ----
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---- n bit shift register for the x operand of the multiplier ----
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---- with bit output ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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-- shift register for the x operand of the multiplier
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-- outputs the lsb of the register or bit at offset according to the
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-- selected pipeline part
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entity x_shift_reg is
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entity x_shift_reg is
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generic(
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generic(
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n : integer := 1536;
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n : integer := 1536; -- width of the operands (# bits)
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t : integer := 48;
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t : integer := 48; -- total number of stages
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tl : integer := 16
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tl : integer := 16 -- lower number of stages
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);
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);
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port(
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port(
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-- clock input
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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-- x operand in (n-bit)
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x_in : in std_logic_vector((n-1) downto 0);
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x_in : in std_logic_vector((n-1) downto 0);
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load_x : in std_logic;
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-- control signals
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next_x : in std_logic;
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reset : in std_logic; -- reset, clears register
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p_sel : in std_logic_vector(1 downto 0);
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load_x : in std_logic; -- load operand into shift register
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next_x : in std_logic; -- next bit of x
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p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
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-- x operand bit out (serial)
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x_i : out std_logic
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x_i : out std_logic
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);
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);
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end x_shift_reg;
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end x_shift_reg;
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architecture Behavioral of x_shift_reg is
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architecture Behavioral of x_shift_reg is
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signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
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signal x_reg : std_logic_vector((n-1) downto 0); -- register
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constant s : integer := n/t; -- nr of stages
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constant s : integer := n/t; -- stage width
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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begin
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begin
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REG_PROC: process(reset, clk)
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REG_PROC: process(reset, clk)
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begin
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begin
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if reset = '1' then -- Reset, clear the register
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if reset = '1' then -- Reset, clear the register
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x_reg_i <= (others => '0');
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x_reg <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if load_x = '1' then -- Load_x, load the register with x_in
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if load_x = '1' then -- Load_x, load the register with x_in
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x_reg_i <= x_in;
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x_reg <= x_in;
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elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
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elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
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x_reg_i((n-2) downto 0) <= x_reg_i((n-1) downto 1);
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x_reg((n-2) downto 0) <= x_reg((n-1) downto 1);
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else -- else remember state
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else -- else remember state
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x_reg_i <= x_reg_i;
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x_reg <= x_reg;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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with p_sel select -- pipeline select
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with p_sel select -- pipeline select
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x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
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x_i <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
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x_reg_i(0) when others; -- use LS bit for lower part of pipeline
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x_reg(0) when others; -- use LS bit for lower part of pipeline
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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