| Line 98... |
Line 98... |
C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- Bus protocol parameters
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-- Bus protocol parameters
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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| Line 286... |
Line 286... |
|
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-- implement slave register
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-- implement slave register
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SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is
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SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is
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begin
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begin
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if rising_edge(S_AXI_ACLK) then
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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if reset = '1' then
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slv_reg <= (others => '0');
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slv_reg <= (others => '0');
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elsif load_flags = '1' then
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elsif load_flags = '1' then
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slv_reg <= slv_reg(31 downto 16) & core_flags;
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slv_reg <= slv_reg(31 downto 16) & core_flags;
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else
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else
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if (slv_reg_write_enable='1') then
|
if (slv_reg_write_enable='1') then
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| Line 304... |
Line 304... |
core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
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core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
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IntrEvent <= core_interrupt;
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IntrEvent <= core_interrupt;
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|
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FLAGS_CNTRL_PROC : process(S_AXI_ACLK, S_AXI_ARESETN) is
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FLAGS_CNTRL_PROC : process(S_AXI_ACLK, S_AXI_ARESETN) is
|
begin
|
begin
|
if S_AXI_ARESETN = '0' then
|
if reset = '1' then
|
core_flags <= (others => '0');
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core_flags <= (others => '0');
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load_flags <= '0';
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load_flags <= '0';
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elsif rising_edge(S_AXI_ACLK) then
|
elsif rising_edge(S_AXI_ACLK) then
|
if core_start = '1' then
|
if core_start = '1' then
|
core_flags <= (others => '0');
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core_flags <= (others => '0');
|
