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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
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);
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);
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port(
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port(
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--USER ports
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--USER ports
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calc_time : out std_logic;
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calc_time : out std_logic;
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IntrEvent : out std_logic;
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IntrEvent : out std_logic;
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core_clk : in std_logic;
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-------------------------
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-------------------------
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-- AXI4lite interface
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-- AXI4lite interface
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-------------------------
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-------------------------
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--- Global signals
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--- Global signals
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S_AXI_ACLK : in std_logic;
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S_AXI_ACLK : in std_logic;
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_MEM_STYLE => C_MEM_STYLE,
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C_MEM_STYLE => C_MEM_STYLE,
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C_FPGA_MAN => C_FPGA_MAN
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C_FPGA_MAN => C_FPGA_MAN
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)
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)
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port map(
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port map(
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clk => S_AXI_ACLK,
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bus_clk => S_AXI_ACLK,
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core_clk => core_clk,
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reset => reset,
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reset => reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable => core_write_enable,
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write_enable => core_write_enable,
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data_in => S_AXI_WDATA(31 downto 0),
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data_in => S_AXI_WDATA(31 downto 0),
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rw_address => core_rw_address,
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rw_address => core_rw_address,
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