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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Diff between revs 89 and 90

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Rev 89 Rev 90
Line 110... Line 110... 
  );
 
  );
 
  port(
 
  port(
 
    --USER ports
 
    --USER ports
 
    calc_time                     : out std_logic;
 
    calc_time                     : out std_logic;
 
    IntrEvent                     : out std_logic;
 
    IntrEvent                     : out std_logic;
 
    core_clk                      : in std_logic;
 
 
 
    -------------------------
 
    -------------------------
 
    -- AXI4lite interface
 
    -- AXI4lite interface
 
    -------------------------
 
    -------------------------
 
    --- Global signals
 
    --- Global signals
 
    S_AXI_ACLK                     : in  std_logic;
 
    S_AXI_ACLK                     : in  std_logic;
Line 386... Line 385... 
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
 
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
 
    C_MEM_STYLE       => C_MEM_STYLE,
 
    C_MEM_STYLE       => C_MEM_STYLE,
 
    C_FPGA_MAN        => C_FPGA_MAN
 
    C_FPGA_MAN        => C_FPGA_MAN
 
  )
 
  )
 
  port map(
 
  port map(
 
    bus_clk   => S_AXI_ACLK,
 
    clk   => S_AXI_ACLK,
 
    core_clk  => core_clk,
 
 
 
    reset => reset,
 
    reset => reset,
 
      -- operand memory interface (plb shared memory)
 
      -- operand memory interface (plb shared memory)
 
    write_enable => core_write_enable,
 
    write_enable => core_write_enable,
 
    data_in      => S_AXI_WDATA(31 downto 0),
 
    data_in      => S_AXI_WDATA(31 downto 0),
 
    rw_address   => core_rw_address,
 
    rw_address   => core_rw_address,

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