Line 97... |
Line 97... |
-- Multiplier parameters
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-- Multiplier parameters
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_AW : integer := 7;
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- Bus protocol parameters
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-- Bus protocol parameters
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector := X"00000000"
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C_HIGHADDR : std_logic_vector := X"00000000"
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);
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);
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port(
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port(
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--USER ports
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--USER ports
|
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core_clk : in std_logic;
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calc_time : out std_logic;
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calc_time : out std_logic;
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IntrEvent : out std_logic;
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IntrEvent : out std_logic;
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-------------------------
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-------------------------
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-- AXI4lite interface
|
-- AXI4lite interface
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-------------------------
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-------------------------
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Line 392... |
Line 393... |
generic map(
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_AW => C_FIFO_AW,
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C_MEM_STYLE => C_MEM_STYLE,
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C_MEM_STYLE => C_MEM_STYLE,
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C_FPGA_MAN => C_FPGA_MAN
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C_FPGA_MAN => C_FPGA_MAN
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)
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)
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port map(
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port map(
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clk => S_AXI_ACLK,
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bus_clk => S_AXI_ACLK,
|
|
core_clk => core_clk,
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reset => reset,
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reset => reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable => core_write_enable,
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write_enable => core_write_enable,
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data_in => S_AXI_WDATA(31 downto 0),
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data_in => S_AXI_WDATA(31 downto 0),
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rw_address => core_rw_address,
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rw_address => core_rw_address,
|