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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Diff between revs 91 and 94

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Rev 91 Rev 94
Line 97... Line 97...
    -- Multiplier parameters
    -- Multiplier parameters
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true;
    C_SPLIT_PIPELINE  : boolean := true;
    C_FIFO_DEPTH      : integer := 32;
    C_FIFO_AW         : integer := 7;
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    -- Bus protocol parameters
    -- Bus protocol parameters
    C_S_AXI_DATA_WIDTH             : integer              := 32;
    C_S_AXI_DATA_WIDTH             : integer              := 32;
    C_S_AXI_ADDR_WIDTH             : integer              := 32;
    C_S_AXI_ADDR_WIDTH             : integer              := 32;
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
    C_HIGHADDR                     : std_logic_vector     := X"00000000"
    C_HIGHADDR                     : std_logic_vector     := X"00000000"
  );
  );
  port(
  port(
    --USER ports
    --USER ports
 
    core_clk                      : in std_logic;
    calc_time                     : out std_logic;
    calc_time                     : out std_logic;
    IntrEvent                     : out std_logic;
    IntrEvent                     : out std_logic;
    -------------------------
    -------------------------
    -- AXI4lite interface
    -- AXI4lite interface
    -------------------------
    -------------------------
Line 392... Line 393...
  generic map(
  generic map(
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
    C_FIFO_AW         => C_FIFO_AW,
    C_MEM_STYLE       => C_MEM_STYLE,
    C_MEM_STYLE       => C_MEM_STYLE,
    C_FPGA_MAN        => C_FPGA_MAN
    C_FPGA_MAN        => C_FPGA_MAN
  )
  )
  port map(
  port map(
    clk   => S_AXI_ACLK,
    bus_clk   => S_AXI_ACLK,
 
    core_clk  => core_clk,
    reset => reset,
    reset => reset,
      -- operand memory interface (plb shared memory)
      -- operand memory interface (plb shared memory)
    write_enable => core_write_enable,
    write_enable => core_write_enable,
    data_in      => S_AXI_WDATA(31 downto 0),
    data_in      => S_AXI_WDATA(31 downto 0),
    rw_address   => core_rw_address,
    rw_address   => core_rw_address,

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