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Line 93... |
entity user_logic is
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entity user_logic is
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generic
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generic
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(
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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--USER generics added here
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--USER generics added here
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-- Multiplier parameters
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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-- Bus protocol parameters, do not add to or delete
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C_SLV_AWIDTH : integer := 32;
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C_SLV_AWIDTH : integer := 32;
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Line 393... |
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------------------------------------------
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------------------------------------------
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-- Multiplier core instance
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-- Multiplier core instance
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------------------------------------------
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------------------------------------------
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the_multiplier: mod_sim_exp_core
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the_multiplier: mod_sim_exp_core
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port map( clk => Bus2IP_Clk, -- v
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generic map(
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reset => Bus2IP_Reset, -- v
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
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)
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port map(
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clk => Bus2IP_Clk,
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reset => Bus2IP_Reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable => core_write_enable,
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write_enable => core_write_enable,
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data_in => core_data_in,
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data_in => core_data_in,
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rw_address => core_rw_address,
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rw_address => core_rw_address,
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data_out => core_data_out,
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data_out => core_data_out,
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collision => core_mem_collision, -- v
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collision => core_mem_collision,
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-- op_sel fifo interface
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-- op_sel fifo interface
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fifo_din => core_fifo_din,
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fifo_din => core_fifo_din,
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fifo_push => core_fifo_push,
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fifo_push => core_fifo_push,
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fifo_full => core_fifo_full, -- v
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fifo_full => core_fifo_full,
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fifo_nopush => core_fifo_nopush, -- v
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fifo_nopush => core_fifo_nopush,
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-- ctrl signals
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-- ctrl signals
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start => core_start, -- v
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start => core_start,
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run_auto => core_run_auto, -- v
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run_auto => core_run_auto,
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ready => core_ready, -- v
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ready => core_ready,
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x_sel_single => core_x_sel_single, -- v
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x_sel_single => core_x_sel_single,
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y_sel_single => core_y_sel_single, -- v
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y_sel_single => core_y_sel_single,
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dest_op_single => core_dest_op_single, -- v
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dest_op_single => core_dest_op_single,
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p_sel => core_p_sel, -- v
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p_sel => core_p_sel,
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calc_time => calc_time -- v
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calc_time => calc_time
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);
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);
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------------------------------------------
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------------------------------------------
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-- Drive IP to Bus signals
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-- Drive IP to Bus signals
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------------------------------------------
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------------------------------------------
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IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
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IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
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mem_ip2bus_data when mem_read_ack = '1' else
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mem_ip2bus_data when mem_read_ack = '1' else
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