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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_asym.vhd] - Diff between revs 90 and 94

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Rev 90 Rev 94
Line 60... Line 60...
    rddepth : integer := 4; -- nr of 32-bit words
    rddepth : integer := 4; -- nr of 32-bit words
    wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
    wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
    device  : string  := "xilinx"  -- device template to use
    device  : string  := "xilinx"  -- device template to use
  );
  );
  port  (
  port  (
    clk : in std_logic;
 
    -- write port
    -- write port
    waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
    clkA   : in std_logic;
    we    : in std_logic;
    waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
    din   : in std_logic_vector(wrwidth-1 downto 0);
    weA    : in std_logic;
 
    dinA   : in std_logic_vector(wrwidth-1 downto 0);
    -- read port
    -- read port
    raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
    clkB   : in std_logic;
    dout  : out std_logic_vector(31 downto 0)
    raddrB : in std_logic_vector(log2(rddepth)-1 downto 0);
 
    doutB  : out std_logic_vector(31 downto 0)
  );
  );
end dpram_asym;
end dpram_asym;
 
 
architecture behavorial of dpram_asym is
architecture behavorial of dpram_asym is
  -- constants
  -- constants
Line 80... Line 81...
begin
begin
 
 
  xilinx_device : if device="xilinx" generate
  xilinx_device : if device="xilinx" generate
    -- the memory
    -- the memory
    type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
    type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
    signal RAM : ram_type := (others => (others => '0'));
    shared variable RAM : ram_type := (others => (others => '0'));
 
 
    -- xilinx constraint to use blockram resources
    -- xilinx constraint to use blockram resources
    attribute ram_style : string;
    attribute ram_style : string;
    attribute ram_style of ram:signal is "block";
    attribute ram_style of RAM:variable is "block";
  begin
  begin
    process (clk)
    -- Write port A
 
    process (clkA)
    begin
    begin
      if (clk'event and clk = '1') then
      if rising_edge(clkA) then
        if (we = '1') then
        if (weA = '1') then
          RAM(conv_integer(waddr)) <= din;
          RAM(conv_integer(waddrA)) := dinA;
        end if;
        end if;
 
      end if;
 
    end process;
 
 
 
    -- Read port B
 
    process (clkB)
 
    begin
 
      if rising_edge(clkB) then
        for i in 0 to R-1 loop
        for i in 0 to R-1 loop
          dout((i+1)*wrwidth-1 downto i*wrwidth)
          doutB((i+1)*wrwidth-1 downto i*wrwidth)
                <= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R))));
                <= RAM(conv_integer(raddrB & conv_std_logic_vector(i,log2(R))));
        end loop;
        end loop;
      end if;
      end if;
    end process;
    end process;
  end generate;
  end generate;
 
 
  altera_device : if device="altera" generate
  altera_device : if device="altera" generate
    -- Use a multidimensional array to model mixed-width 
    -- Use a multidimensional array to model mixed-width 
    type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
    type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
    type ram_t is array (0 to rddepth-1) of word_t;
    type ram_t is array (0 to rddepth-1) of word_t;
 
 
    signal ram : ram_t;
    shared variable ram : ram_t;
    signal q_local : word_t;
    signal q_local : word_t;
    -- altera constraints:
    -- altera constraints:
    -- for smal depths:
    -- for smal depths:
    --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
    --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
    --  may be left commented.
    --  may be left commented.
    --  uncomment this attribute if that option is off and you know wich primitives should be used.
    --  uncomment this attribute if that option is off and you know wich primitives should be used.
    --attribute ramstyle : string;
    --attribute ramstyle : string;
    --attribute ramstyle of RAM : signal is "M9K, no_rw_check";
    --attribute ramstyle of RAM : signal is "M9K, no_rw_check";
  begin
  begin
    unpack: for i in 0 to R - 1 generate
    unpack: for i in 0 to R - 1 generate
      dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
      doutB(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
    end generate unpack;
    end generate unpack;
 
 
    process(clk, we)
    process(clkA)
    begin
    begin
      if(rising_edge(clk)) then
      if(rising_edge(clkA)) then
        if(we = '1') then
        if(weA = '1') then
          ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din;
          ram(conv_integer(waddrA)/R)(conv_integer(waddrA) mod R) := dinA;
        end if;
        end if;
        q_local <= ram(conv_integer(raddr));
      end if;
 
    end process;
 
 
 
    process(clkB)
 
    begin
 
      if(rising_edge(clkB)) then
 
        q_local <= ram(conv_integer(raddrB));
      end if;
      end if;
    end process;
    end process;
  end generate;
  end generate;
 
 
end behavorial;
end behavorial;

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