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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_generic.vhd] - Diff between revs 90 and 94

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Line 54... Line 54...
entity dpram_generic is
entity dpram_generic is
  generic (
  generic (
    depth : integer := 2
    depth : integer := 2
  );
  );
  port  (
  port  (
    clk : in std_logic;
    -- write port A
    -- write port
    clkA   : in std_logic;
    waddr : in std_logic_vector(log2(depth)-1 downto 0);
    waddrA : in std_logic_vector(log2(depth)-1 downto 0);
    we    : in std_logic;
    weA    : in std_logic;
    din   : in std_logic_vector(31 downto 0);
    dinA   : in std_logic_vector(31 downto 0);
    -- read port
    -- read port B
    raddr : in std_logic_vector(log2(depth)-1 downto 0);
    clkB   : in std_logic;
    dout  : out std_logic_vector(31 downto 0)
    raddrB : in std_logic_vector(log2(depth)-1 downto 0);
 
    doutB  : out std_logic_vector(31 downto 0)
  );
  );
end dpram_generic;
end dpram_generic;
 
 
architecture behavorial of dpram_generic is
architecture behavorial of dpram_generic is
  -- the memory
  -- the memory
  type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
  type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
  signal RAM : ram_type := (others => (others => '0'));
  shared variable RAM : ram_type := (others => (others => '0'));
 
 
  -- xilinx constraint to use blockram resources
  -- xilinx constraint to use blockram resources
  attribute ram_style : string;
  attribute ram_style : string;
  attribute ram_style of ram:signal is "block";
  attribute ram_style of ram:variable is "block";
  -- altera constraints:
  -- altera constraints:
  -- for smal depths:
  -- for smal depths:
  --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
  --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
  --  may be left commented.
  --  may be left commented.
  --  uncomment this attribute if that option is off and you know wich primitives should be used.
  --  uncomment this attribute if that option is off and you know wich primitives should be used.
  --attribute ramstyle : string;
  --attribute ramstyle : string;
  --attribute ramstyle of RAM : signal is "M9K, no_rw_check";
  --attribute ramstyle of RAM : variable is "M9K, no_rw_check";
begin
begin
  process (clk)
  process (clkA)
  begin
  begin
    if (clk'event and clk = '1') then
    if rising_edge(clkA) then
      if (we = '1') then
      if (weA = '1') then
        RAM(conv_integer(waddr)) <= din;
        RAM(conv_integer(waddrA)) := dinA;
      end if;
      end if;
      dout <= RAM(conv_integer(raddr));
 
    end if;
    end if;
  end process;
  end process;
 
 
 
  process (clkB)
 
  begin
 
    if rising_edge(clkB) then
 
      doutB <= RAM(conv_integer(raddrB));
 
    end if;
 
  end process;
 
 
end behavorial;
end behavorial;
 
 
 
 
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