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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_generic.vhd] - Diff between revs 60 and 61

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Line 72... Line 72...
end tdpram_generic;
end tdpram_generic;
 
 
architecture behavorial of tdpram_generic is
architecture behavorial of tdpram_generic is
  -- the memory
  -- the memory
  type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
  type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
  shared variable RAM: ram_type;
  shared variable RAM: ram_type := (others => (others => '0'));
 
 
  -- xilinx constraint to use blockram resources
  -- xilinx constraint to use blockram resources
  attribute ram_style : string;
  attribute ram_style : string;
  attribute ram_style of RAM:variable is "block";
  attribute ram_style of RAM:variable is "block";
  -- altera constraints:
  -- altera constraints:
  -- for smal depths:
  -- for smal depths:
  --  if the synthesis option : allow any size of RAM to be inferred, is on these lines 
  --  if the synthesis option "allow any size of RAM to be inferred" is on, these lines 
  --  may be left uncommented.
  --  may be left commented.
  --  uncomment this attribute if that option is of and you know wich primitives should be used.
  --  uncomment this attribute if that option is off and you know wich primitives should be used.
  --attribute ramstyle : string;
  --attribute ramstyle : string;
  --attribute ramstyle of ram : signal is "M9K, no_rw_check";
  --attribute ramstyle of RAM : signal is "M9K, no_rw_check";
begin
begin
  -- port A
  -- port A
  process (clkA)
  process (clkA)
  begin
  begin
    if (clkA'event and clkA = '1') then
    if (clkA'event and clkA = '1') then

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