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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_generic.vhd] - Diff between revs 60 and 61
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Rev 61 |
| Line 72... |
Line 72... |
end tdpram_generic;
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end tdpram_generic;
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architecture behavorial of tdpram_generic is
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architecture behavorial of tdpram_generic is
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-- the memory
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-- the memory
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type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
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type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
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shared variable RAM: ram_type;
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shared variable RAM: ram_type := (others => (others => '0'));
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-- xilinx constraint to use blockram resources
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-- xilinx constraint to use blockram resources
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attribute ram_style : string;
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attribute ram_style : string;
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attribute ram_style of RAM:variable is "block";
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attribute ram_style of RAM:variable is "block";
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-- altera constraints:
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-- altera constraints:
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-- for smal depths:
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-- for smal depths:
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-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
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-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
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-- may be left uncommented.
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-- may be left commented.
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-- uncomment this attribute if that option is of and you know wich primitives should be used.
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-- uncomment this attribute if that option is off and you know wich primitives should be used.
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--attribute ramstyle : string;
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--attribute ramstyle : string;
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--attribute ramstyle of ram : signal is "M9K, no_rw_check";
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--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
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begin
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begin
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-- port A
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-- port A
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process (clkA)
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process (clkA)
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begin
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begin
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if (clkA'event and clkA = '1') then
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if (clkA'event and clkA = '1') then
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