| Line 20... |
Line 20... |
$(HDL_DIR)/core/first_stage.vhd \
|
$(HDL_DIR)/core/first_stage.vhd \
|
$(HDL_DIR)/core/last_stage.vhd \
|
$(HDL_DIR)/core/last_stage.vhd \
|
$(HDL_DIR)/core/modulus_ram.vhd \
|
$(HDL_DIR)/core/modulus_ram.vhd \
|
$(HDL_DIR)/core/mont_ctrl.vhd \
|
$(HDL_DIR)/core/mont_ctrl.vhd \
|
$(HDL_DIR)/core/mont_mult_sys_pipeline.vhd \
|
$(HDL_DIR)/core/mont_mult_sys_pipeline.vhd \
|
$(HDL_DIR)/core/multiplier_core.vhd \
|
$(HDL_DIR)/core/mod_sim_exp_core.vhd \
|
$(HDL_DIR)/core/operand_dp.vhd \
|
$(HDL_DIR)/core/operand_dp.vhd \
|
$(HDL_DIR)/core/operand_mem.vhd \
|
$(HDL_DIR)/core/operand_mem.vhd \
|
$(HDL_DIR)/core/operand_ram.vhd \
|
$(HDL_DIR)/core/operand_ram.vhd \
|
$(HDL_DIR)/core/operands_sp.vhd \
|
$(HDL_DIR)/core/operands_sp.vhd \
|
$(HDL_DIR)/core/register_1b.vhd \
|
$(HDL_DIR)/core/register_1b.vhd \
|
| Line 38... |
Line 38... |
|
|
##
|
##
|
# Testbench HDL file
|
# Testbench HDL file
|
##
|
##
|
TB_SRC_DIR = ../bench/vhdl/
|
TB_SRC_DIR = ../bench/vhdl/
|
TB_SRC = $(TB_SRC_DIR)tb_multiplier_core.vhd
|
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
|
|
|
#######################################
|
#######################################
|
all: mod_sim_exp
|
all: mod_sim_exp
|
|
|
clean:
|
clean:
|
| Line 67... |
Line 67... |
#echo building Modular Exponentiation Core Testbench
|
#echo building Modular Exponentiation Core Testbench
|
#echo --
|
#echo --
|
vcom $(VCOMOPS) -work work $(TB_SRC)
|
vcom $(VCOMOPS) -work work $(TB_SRC)
|
|
|
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
|
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
|
vsim -c -do mod_sim_exp.do -lib work tb_multiplier_core
|
vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
|
vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
|
vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
|
