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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_alu16.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 154... Line 154...
-- Seth Henry      07/19/06 Design Start
-- Seth Henry      07/19/06 Design Start
-- Seth Henry      03/13/15 Added "Almost Equal" instruction
-- Seth Henry      03/13/15 Added "Almost Equal" instruction
-- Seth Henry      12/19/19 Renamed to o8_alu16 to fit "theme"
-- Seth Henry      12/19/19 Renamed to o8_alu16 to fit "theme"
-- Seth Henry      04/10/20 Comment and code cleanup
-- Seth Henry      04/10/20 Comment and code cleanup
-- Seth Henry      04/16/20 Modified to use Open8 bus record
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
Line 170... Line 171...
generic(
generic(
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '0';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic
  Interrupt                  : out std_logic
);
);
end entity;
end entity;
 
 
Line 243... Line 245...
 
 
  constant User_Addr         : std_logic_vector(15 downto 5):=
  constant User_Addr         : std_logic_vector(15 downto 5):=
                                 Address(15 downto 5);
                                 Address(15 downto 5);
  alias Comp_Addr            is Open8_Bus.Address(15 downto 5);
  alias Comp_Addr            is Open8_Bus.Address(15 downto 5);
 
 
  signal Reg_Addr            : std_logic_vector(4 downto 0) :=
 
                                (others => '0');
 
 
 
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
  signal Wr_En               : std_logic := '0';
 
  signal Wr_Data_q           : DATA_TYPE := (others => '0');
  alias  Reg_Sel_d           is Open8_Bus.Address(4 downto 0);
  signal Rd_En               : std_logic := '0';
  signal Reg_Sel_q           : std_logic_vector(4 downto 0) := "00000";
 
  signal Wr_En_d             : std_logic := '0';
 
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
 
  signal Wr_Data_q           : DATA_TYPE := x"00";
 
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
  type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
  signal regfile             : REG_ARRAY := (
  signal regfile             : REG_ARRAY := (
                                 x"0000",x"0000",x"0000",x"0000",
                                 x"0000",x"0000",x"0000",x"0000",
                                 x"0000",x"0000",x"0000",x"0000");
                                 x"0000",x"0000",x"0000",x"0000");
Line 371... Line 376...
                                (others => '0');
                                (others => '0');
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  -- Sign-extend the base operands to created operands for signed math
  -- Sign-extend the base operands to created operands for signed math
  S_Operand_1                <= signed(Operand_1(15) & Operand_1);
  S_Operand_1                <= signed(Operand_1(15) & Operand_1);
  S_Operand_2                <= signed(Operand_2(15) & Operand_2);
  S_Operand_2                <= signed(Operand_2(15) & Operand_2);
 
 
Line 394... Line 401...
  ALU_proc: process( Clock, Reset )
  ALU_proc: process( Clock, Reset )
    variable Reg_Sel         : integer;
    variable Reg_Sel         : integer;
    variable Oper_Sel        : integer;
    variable Oper_Sel        : integer;
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Wr_En                  <= '0';
      Reg_Sel_q              <= (others => '0');
      Wr_Data_q              <= (others => '0');
      Wr_En_q                <= '0';
      Rd_En                  <= '0';
      Wr_Data_q              <= x"00";
 
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Reg_Addr               <= (others => '0');
 
      Opcode                 <= (others => '0');
      Opcode                 <= (others => '0');
      Operand_Sel            <= (others => '0');
      Operand_Sel            <= (others => '0');
      Tolerance              <= (others => '0');
      Tolerance              <= (others => '0');
      Start                  <= '0';
      Start                  <= '0';
      Busy_q                 <= '0';
      Busy_q                 <= '0';
Line 433... Line 440...
      count                  <= DIV_WIDTH;
      count                  <= DIV_WIDTH;
      IDIV_Busy              <= '0';
      IDIV_Busy              <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      -- For convenience, convert these to integers and assign them to
      -- For convenience, convert these to integers and assign them to
      --  variables
      --  variables
      Reg_Sel                := conv_integer(Reg_Addr(3 downto 1));
      Reg_Sel                := conv_integer(Reg_Sel_q(3 downto 1));
      Oper_Sel               := conv_integer(Operand_Sel);
      Oper_Sel               := conv_integer(Operand_Sel);
 
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_En_q                <= Wr_En_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Wr_Data_q              <= Wr_Data_d;
      Reg_Addr               <= Open8_Bus.Address(4 downto 0);
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Start                  <= '0';
      Start                  <= '0';
      if( Wr_En = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Addr )is
        case( Reg_Sel_q )is
          -- Even addresses go to the lower byte of the register
          -- Even addresses go to the lower byte of the register
          when "00000" | "00010" | "00100" | "00110" |
          when "00000" | "00010" | "00100" | "00110" |
               "01000" | "01010" | "01100" | "01110" =>
               "01000" | "01010" | "01100" | "01110" =>
            regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
            regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
 
 
Line 470... Line 477...
 
 
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      if( Rd_En_q = '1' )then
 
        case( Reg_Sel_q )is
      if( Rd_En = '1' )then
 
        case( Reg_Addr )is
 
          when "00000" | "00010" | "00100" | "00110" |
          when "00000" | "00010" | "00100" | "00110" |
               "01000" | "01010" | "01100" | "01110" =>
               "01000" | "01010" | "01100" | "01110" =>
            Rd_Data          <= regfile(Reg_Sel)(7 downto 0);
            Rd_Data          <= regfile(Reg_Sel)(7 downto 0);
          when "00001" | "00011" | "00101" | "00111" |
          when "00001" | "00011" | "00101" | "00111" |
               "01001" | "01011" | "01101" | "01111" =>
               "01001" | "01011" | "01101" | "01111" =>

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