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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 65... Line 65...
 
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
 
 
  signal Rd_En               : std_logic := '0';
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  constant Threshold_bits    : integer := ceil_log2(Threshold_Count);
  constant Threshold_bits    : integer := ceil_log2(Threshold_Count);
  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
                        conv_std_logic_vector(Threshold_Count,Threshold_bits);
                        conv_std_logic_vector(Threshold_Count,Threshold_bits);
 
 
Line 88... Line 89...
  signal Ref_Detect_q1       : std_logic := '0';
  signal Ref_Detect_q1       : std_logic := '0';
  signal Ref_Detect_CoS      : std_logic := '0';
  signal Ref_Detect_CoS      : std_logic := '0';
 
 
begin
begin
 
 
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Rd_En                  <= Addr_Match;
      Rd_En_q                <= Rd_En_d;
 
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
      if( Rd_En_q = '1' )then
        Rd_Data(6)           <= Ref_In_q2;
        Rd_Data(6)           <= Ref_In_q2;
        Rd_Data(7)           <= Ref_Detect;
        Rd_Data(7)           <= Ref_Detect;
      end if;
      end if;
 
 
    end if;
    end if;

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