| Line 72... |
Line 72... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
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-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
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-- Seth Henry 06/14/11 Fixed STO instruction to avoid register corruption
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-- Fixed interrupt logic to avoid address corruption
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-- when interrupt coincides with branch instruction
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 582... |
Line 579... |
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signal i_Ints : INTERRUPT_BUNDLE := (others => '0');
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signal i_Ints : INTERRUPT_BUNDLE := (others => '0');
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signal Pending_D : INTERRUPT_BUNDLE := (others => '0');
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signal Pending_D : INTERRUPT_BUNDLE := (others => '0');
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signal Pending : INTERRUPT_BUNDLE := (others => '0');
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signal Pending : INTERRUPT_BUNDLE := (others => '0');
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_FSM : std_logic := '0';
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signal Mask : std_logic_vector(6 downto 0) := (others => '0');
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signal ISR_D, ISR_Q : ADDRESS_TYPE := (others => '0');
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signal ISR_D, ISR_Q : ADDRESS_TYPE := (others => '0');
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type INT_HIST is array (0 to 8) of integer range 0 to 7;
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type INT_HIST is array (0 to 8) of integer range 0 to 7;
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signal History : INT_HIST := (others => 0);
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signal History : INT_HIST := (others => 0);
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signal Int_Trig : std_logic := '0';
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signal Int_Trig : std_logic := '0';
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signal Hist_Level : integer range 0 to 7 := 0;
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signal Hist_Level : integer range 0 to 7 := 0;
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signal Hist_Ptr : integer range 0 to 8 := 0;
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signal Hist_Ptr : integer range 0 to 8 := 0;
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begin
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begin
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Int_Mask <= Mask & '1';
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ISR <= ISR_Q;
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ISR <= ISR_Q;
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Int_Mask_proc: process( Mask, Interrupts, INT_Ctrl )
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Int_Mask_proc: process( Int_Mask, Interrupts, INT_Ctrl )
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variable S_Mask : std_logic_vector(7 downto 0);
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variable S_Mask : std_logic_vector(7 downto 0);
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begin
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begin
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S_Mask := Mask & '1';
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S_Mask := Int_Mask;
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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i_Ints(i) <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i))
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i_Ints(i) <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i))
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and S_Mask(i);
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and S_Mask(i);
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end loop;
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end loop;
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end process;
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end process;
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| Line 677... |
Line 673... |
begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Int_Req <= '0';
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Int_Req <= '0';
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Pending <= x"00";
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Pending <= x"00";
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Wait_for_FSM <= '0';
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Wait_for_FSM <= '0';
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Mask <= Default_Interrupt_Mask(7 downto 1);
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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ISR_Q <= INT_VECTOR_0;
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ISR_Q <= INT_VECTOR_0;
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for i in 0 to 8 loop
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for i in 0 to 8 loop
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History(i) <= 0;
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History(i) <= 0;
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end loop;
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end loop;
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Hist_Ptr <= 0;
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Hist_Ptr <= 0;
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| Line 695... |
Line 691... |
-- Set the Wait_for_FSM flag on Int_Trig
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-- Set the Wait_for_FSM flag on Int_Trig
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elsif( Int_Trig = '1' )then
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elsif( Int_Trig = '1' )then
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Wait_for_FSM <= '1';
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Wait_for_FSM <= '1';
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end if;
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end if;
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if( INT_Ctrl.Mask_Set = '1' )then
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if( INT_Ctrl.Mask_Set = '1' )then
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Mask <= INT_Ctrl.Mask_Data(7 downto 1);
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Int_Mask <= INT_Ctrl.Mask_Data(7 downto 1) & '1';
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end if;
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end if;
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ISR_Q <= ISR_D;
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ISR_Q <= ISR_D;
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if( Int_Trig = '1' )then
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if( Int_Trig = '1' )then
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History(Hist_Ptr+1) <= Hist_Level;
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History(Hist_Ptr+1) <= Hist_Level;
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Hist_Ptr <= Hist_Ptr + 1;
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Hist_Ptr <= Hist_Ptr + 1;
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| Line 1332... |
Line 1328... |
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-- Interrupt service routines can only begin during the decode and wait
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-- Interrupt service routines can only begin during the decode and wait
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-- states to avoid corruption due to incomplete instruction execution
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-- states to avoid corruption due to incomplete instruction execution
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if( Int_Req = '1' )then
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if( Int_Req = '1' )then
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if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
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if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
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CPU_Next_State <= ISR_C1;
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-- Reset all of the sub-block controls to IDLE, to avoid unintended
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PC_Ctrl.Oper <= PC_INCR;
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-- operation due to the current instruction
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ALU_Ctrl.Oper <= ALU_IDLE;
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Cache_Ctrl <= CACHE_IDLE;
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SP_Ctrl.Oper <= SP_IDLE;
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-- Rewind the PC by 3 to compensate for the pipeline registers
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-- Rewind the PC by 3 to compensate for the pipeline registers
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= x"FF";
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PC_Ctrl.Offset <= x"FF";
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CPU_Next_State <= ISR_C1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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