-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Entity: o8_hd44780_4b
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-- VHDL Entity: o8_hd44780_4b
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-- Description: Provides low-level access to a "standard" character LCD using
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-- Description: Provides low-level access to a "standard" character LCD using
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-- the ST/HD44780(U) control ASIC wired in reduced (4-bit) mode.
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-- the ST/HD44780(U) control ASIC wired in reduced (4-bit) mode.
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-- All low-level timing of the control signals are handled by this
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-- All low-level timing of the control signals are handled by this
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-- module, allowing client firmware to use a simple register
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-- module, allowing client firmware to use a simple register
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-- interface to program the LCD panel.
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-- interface to program the LCD panel.
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-- Init routine initializes the display and displays a single
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-- Init routine initializes the display and displays a single
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-- character to demonstrate correct function, then listens for
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-- character to demonstrate correct function, then listens for
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-- user data on its external interface.
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-- user data on its external interface.
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--
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--
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-- Register Map
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-- Register Map
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-- Address Function
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-- Address Function
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA LCD Register Write (Write-only)
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-- 0x0 AAAAAAAA LCD Register Write (Read-Write*)
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-- 0x1 AAAAAAAA LCD Data Write (Write-only)
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-- 0x1 AAAAAAAA LCD Data Write (Read-Write*)
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-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
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-- 0x2 AAAAAAAA LCD Contrast (Read-Write)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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-- 0x3 AAAAAAAA LCD Backlight (Read-Write)
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--
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--
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-- Note: Reading 0x0 or 0x1 will report whether the panel is ready or not in the
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-- MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD Controller
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-- LCD Controller
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- LCD Instruction Set
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-- LCD Instruction Set
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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-- Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Time
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Clear Display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Entry Mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Display Pwr | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Cursor/Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Function Set | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set CGRAM Address | 0 | 0 | 0 | 1 | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- Set DDRAM Address | 0 | 0 | 1 | A | A | A | A | A | A | A | 37uS
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-- Notes:
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-- Notes:
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- S = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
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-- D = Display On/Off (1 = on, 0 = off)
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-- D = Display On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- C = Cursor On/Off (1 = on, 0 = off)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- B = Cursor Blink (1 = block cursor, 0 = underline cursor)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- F = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- N = Number of Lines (0 = 1 lines, 1 = 2 lines)
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
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-- A = Address (see data sheet for usage)
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-- A = Address (see data sheet for usage)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 01/22/13 Design Start
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/10/20 Code & comment cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_hd44780_4b is
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entity o8_hd44780_4b is
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generic(
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generic(
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Use_Contrast : boolean;
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Use_Contrast : boolean;
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Default_Contrast : std_logic_vector(7 downto 0);
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Default_Contrast : std_logic_vector(7 downto 0);
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Use_Backlight : boolean;
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Use_Backlight : boolean;
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Default_Brightness : std_logic_vector(7 downto 0);
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Default_Brightness : std_logic_vector(7 downto 0);
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Clock_Frequency : real;
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Clock_Frequency : real;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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--
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LCD_E : out std_logic;
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LCD_E : out std_logic;
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LCD_RW : out std_logic;
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LCD_RW : out std_logic;
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LCD_RS : out std_logic;
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LCD_RS : out std_logic;
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LCD_D : out std_logic_vector(7 downto 4);
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LCD_D : out std_logic_vector(7 downto 4);
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LCD_CN : out std_logic;
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LCD_CN : out std_logic;
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LCD_BL : out std_logic
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LCD_BL : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_hd44780_4b is
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architecture behave of o8_hd44780_4b is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Valid : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Data : std_logic_vector(7 downto 0) := x"00";
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signal Reg_Data : std_logic_vector(7 downto 0) := x"00";
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signal Tx_Ready : std_logic := '0';
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signal Tx_Ready : std_logic := '0';
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constant LCD_CONFIG1 : std_logic_vector(7 downto 4) := x"3"; -- Init to 4-bit mode
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constant LCD_CONFIG1 : std_logic_vector(7 downto 4) := x"3"; -- Init to 4-bit mode
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constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
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constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
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constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
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constant LCD_CONFIG7 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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constant LCD_CONFIG7 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
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signal init_count : std_logic_vector(2 downto 0) := (others => '0');
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signal init_count : std_logic_vector(2 downto 0) := (others => '0');
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constant INIT_40MS : integer := 40000;
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constant INIT_40MS : integer := 40000;
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_BITS : integer := ceil_log2(INIT_40MS);
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant INIT_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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conv_std_logic_vector(INIT_40MS,INIT_BITS);
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-- For "long" instructions, such as clear display and return home, we need to wait for more
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-- For "long" instructions, such as clear display and return home, we need to wait for more
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-- than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
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-- than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
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constant CLDSP_2MS : integer := 2000;
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constant CLDSP_2MS : integer := 2000;
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constant CLDSP_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant CLDSP_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
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conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
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-- For some reason, we are required to wait 80uS before checking the busy flag, despite
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-- For some reason, we are required to wait 80uS before checking the busy flag, despite
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-- most instructions completing in 37uS. No clue as to why, but it works
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-- most instructions completing in 37uS. No clue as to why, but it works
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constant BUSY_50US : integer := 50;
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constant BUSY_50US : integer := 50;
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
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signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
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constant SNH_600NS : integer := integer(Clock_Frequency * 0.000000600);
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constant SNH_600NS : integer := integer(Clock_Frequency * 0.000000600);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_BITS : integer := ceil_log2(SNH_600NS);
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) :=
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signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) :=
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(others => '0');
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(others => '0');
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type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
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type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
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INIT_WAIT, FN_JUMP, IDLE,
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INIT_WAIT, FN_JUMP, IDLE,
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WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
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WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
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BUSY_PREP, BUSY_WAIT,
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BUSY_PREP, BUSY_WAIT,
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ISSUE_INT );
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ISSUE_INT );
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signal io_state : IO_STATES := INIT;
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signal io_state : IO_STATES := INIT;
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signal LCD_Data : DATA_TYPE := x"00";
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signal LCD_Data : DATA_TYPE := x"00";
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signal LCD_Addr : std_logic := '0';
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signal LCD_Addr : std_logic := '0';
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Backlight & Contrast signals
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-- Backlight & Contrast signals
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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signal LCD_Contrast : DATA_TYPE := x"00";
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signal LCD_Contrast : DATA_TYPE := x"00";
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signal LCD_Bright : DATA_TYPE := x"00";
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signal LCD_Bright : DATA_TYPE := x"00";
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begin
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begin
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Open8 Register interface
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-- Open8 Register interface
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= "00";
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Reg_Sel_q <= "00";
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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Reg_Sel <= '0';
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Reg_Sel <= '0';
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Reg_Data <= x"00";
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Reg_Data <= x"00";
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LCD_Contrast <= Default_Contrast;
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LCD_Contrast <= Default_Contrast;
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LCD_Bright <= Default_Brightness;
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LCD_Bright <= Default_Brightness;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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Reg_Valid <= '0';
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Reg_Valid <= '0';
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if( Wr_En_q = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Reg_Valid <= '1';
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Reg_Valid <= '1';
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Reg_Sel <= Reg_Sel_q(0);
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Reg_Sel <= Reg_Sel_q(0);
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Reg_Data <= Wr_Data_q;
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Reg_Data <= Wr_Data_q;
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when "10" =>
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when "10" =>
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LCD_Contrast <= Wr_Data_q;
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LCD_Contrast <= Wr_Data_q;
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when "11" =>
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when "11" =>
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LCD_Bright <= Wr_Data_q;
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LCD_Bright <= Wr_Data_q;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" | "01" =>
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when "00" | "01" =>
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Rd_Data(7) <= Tx_Ready;
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Rd_Data(7) <= Tx_Ready;
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when "10" =>
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when "10" =>
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Rd_Data <= LCD_Contrast;
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Rd_Data <= LCD_Contrast;
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when "11" =>
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when "11" =>
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Rd_Data <= LCD_Bright;
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Rd_Data <= LCD_Bright;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- LCD and Register logic
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-- LCD and Register logic
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LCD_RW <= '0'; -- Permanently wire the RW line low
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LCD_RW <= '0'; -- Permanently wire the RW line low
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LCD_IO: process( Clock, Reset )
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LCD_IO: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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io_state <= INIT;
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io_state <= INIT;
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init_count <= (others => '0');
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init_count <= (others => '0');
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io_timer <= (others => '0');
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io_timer <= (others => '0');
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busy_timer <= (others => '0');
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busy_timer <= (others => '0');
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LCD_Data <= (others => '0');
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LCD_Data <= (others => '0');
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LCD_Addr <= '0';
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LCD_Addr <= '0';
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_RS <= '0';
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LCD_RS <= '0';
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LCD_D <= (others => '0');
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LCD_D <= (others => '0');
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Tx_Ready <= '0';
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Tx_Ready <= '0';
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_RS <= '0';
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LCD_RS <= '0';
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LCD_D <= (others => '0');
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LCD_D <= (others => '0');
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Tx_Ready <= '0';
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Tx_Ready <= '0';
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Interrupt <= '0';
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Interrupt <= '0';
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io_timer <= io_timer - 1;
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io_timer <= io_timer - 1;
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busy_timer <= busy_timer - uSec_Tick;
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busy_timer <= busy_timer - uSec_Tick;
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case( io_state )is
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case( io_state )is
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|
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when INIT =>
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when INIT =>
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busy_timer <= INIT_DELAY;
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busy_timer <= INIT_DELAY;
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init_count <= (others => '1');
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init_count <= (others => '1');
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io_state <= PWR_WAIT;
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io_state <= PWR_WAIT;
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|
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-- We wait for at least 40mS before continuing initalization.
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-- We wait for at least 40mS before continuing initalization.
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when PWR_WAIT =>
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when PWR_WAIT =>
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if( busy_timer = 0 )then
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if( busy_timer = 0 )then
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io_timer <= SNH_DELAY;
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io_timer <= SNH_DELAY;
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io_state <= INIT_S1;
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io_state <= INIT_S1;
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end if;
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end if;
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|
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-- We write out the first init byte as if we were using an 8-bit
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-- We write out the first init byte as if we were using an 8-bit
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-- data bus, with a single cycle. This is an exception, and the
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-- data bus, with a single cycle. This is an exception, and the
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-- rest of the commands are sent using 2-cycle transfers.
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-- rest of the commands are sent using 2-cycle transfers.
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when INIT_S1 =>
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when INIT_S1 =>
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LCD_D <= LCD_CONFIG1;
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LCD_D <= LCD_CONFIG1;
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LCD_E <= '1';
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LCD_E <= '1';
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if( io_timer = 0 )then
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if( io_timer = 0 )then
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io_timer <= SNH_DELAY;
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io_timer <= SNH_DELAY;
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io_state <= INIT_H1;
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io_state <= INIT_H1;
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end if;
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end if;
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|
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when INIT_H1 =>
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when INIT_H1 =>
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LCD_D <= LCD_CONFIG1;
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LCD_D <= LCD_CONFIG1;
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if( io_timer = 0 )then
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if( io_timer = 0 )then
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busy_timer <= BUSY_DELAY;
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busy_timer <= BUSY_DELAY;
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io_state <= INIT_WAIT;
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io_state <= INIT_WAIT;
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end if;
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end if;
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|
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when INIT_WAIT =>
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when INIT_WAIT =>
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if( busy_timer = 0 )then
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if( busy_timer = 0 )then
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io_state <= FN_JUMP;
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io_state <= FN_JUMP;
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end if;
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end if;
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|
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when FN_JUMP =>
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when FN_JUMP =>
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io_state <= WR_PREP;
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io_state <= WR_PREP;
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case( init_count )is
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case( init_count )is
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when "000" =>
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when "000" =>
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io_state <= IDLE;
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io_state <= IDLE;
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when "001" =>
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when "001" =>
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LCD_Addr <= '0';
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LCD_Addr <= '0';
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LCD_Data <= LCD_CONFIG7; -- Reset the Cursor
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LCD_Data <= LCD_CONFIG7; -- Reset the Cursor
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when "010" =>
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when "010" =>
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LCD_Addr <= '1'; -- Print a "*", and
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LCD_Addr <= '1'; -- Print a "*", and
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LCD_Data <= LCD_CONFIG6; -- set RS to 1
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LCD_Data <= LCD_CONFIG6; -- set RS to 1
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when "011" =>
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when "011" =>
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LCD_Data <= LCD_CONFIG5; -- Entry mode
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LCD_Data <= LCD_CONFIG5; -- Entry mode
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when "100" =>
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when "100" =>
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LCD_Data <= LCD_CONFIG4; -- Clear Display
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LCD_Data <= LCD_CONFIG4; -- Clear Display
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when "101" =>
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when "101" =>
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LCD_Data <= LCD_CONFIG3; -- Display control
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LCD_Data <= LCD_CONFIG3; -- Display control
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when "110" | "111" =>
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when "110" | "111" =>
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LCD_Addr <= '0';
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LCD_Addr <= '0';
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LCD_Data <= LCD_CONFIG2; -- Function set
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LCD_Data <= LCD_CONFIG2; -- Function set
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when others => null;
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when others => null;
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end case;
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end case;
|
|
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when IDLE =>
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when IDLE =>
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Tx_Ready <= '1';
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Tx_Ready <= '1';
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if( Reg_Valid = '1' )then
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if( Reg_Valid = '1' )then
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LCD_Addr <= Reg_Sel;
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LCD_Addr <= Reg_Sel;
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LCD_Data <= Reg_Data;
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LCD_Data <= Reg_Data;
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io_state <= WR_PREP;
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io_state <= WR_PREP;
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end if;
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end if;
|
|
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when WR_PREP =>
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when WR_PREP =>
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io_timer <= SNH_DELAY;
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io_timer <= SNH_DELAY;
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io_state <= WR_SETUP_UB;
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io_state <= WR_SETUP_UB;
|
|
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when WR_SETUP_UB =>
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when WR_SETUP_UB =>
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LCD_RS <= LCD_Addr;
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LCD_RS <= LCD_Addr;
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LCD_D <= LCD_Data(7 downto 4);
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LCD_D <= LCD_Data(7 downto 4);
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LCD_E <= '1';
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LCD_E <= '1';
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if( io_timer = 0 )then
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if( io_timer = 0 )then
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io_timer <= SNH_DELAY;
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io_timer <= SNH_DELAY;
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io_state <= WR_HOLD_UB;
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io_state <= WR_HOLD_UB;
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end if;
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end if;
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|
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when WR_HOLD_UB =>
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when WR_HOLD_UB =>
|
LCD_RS <= LCD_Addr;
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LCD_RS <= LCD_Addr;
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LCD_D <= LCD_Data(7 downto 4);
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LCD_D <= LCD_Data(7 downto 4);
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if( io_timer = 0 )then
|
if( io_timer = 0 )then
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LCD_E <= '0';
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LCD_E <= '0';
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io_timer <= SNH_DELAY;
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io_timer <= SNH_DELAY;
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io_state <= WR_SETUP_LB;
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io_state <= WR_SETUP_LB;
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end if;
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end if;
|
|
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when WR_SETUP_LB =>
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when WR_SETUP_LB =>
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LCD_RS <= LCD_Addr;
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LCD_RS <= LCD_Addr;
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LCD_D <= LCD_Data(3 downto 0);
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LCD_D <= LCD_Data(3 downto 0);
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LCD_E <= '1';
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LCD_E <= '1';
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if( io_timer = 0 )then
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if( io_timer = 0 )then
|
io_timer <= SNH_DELAY;
|
io_timer <= SNH_DELAY;
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io_state <= WR_HOLD_LB;
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io_state <= WR_HOLD_LB;
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end if;
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end if;
|
|
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when WR_HOLD_LB =>
|
when WR_HOLD_LB =>
|
LCD_RS <= LCD_Addr;
|
LCD_RS <= LCD_Addr;
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LCD_D <= LCD_Data(3 downto 0);
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LCD_D <= LCD_Data(3 downto 0);
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if( io_timer = 0 )then
|
if( io_timer = 0 )then
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io_state <= BUSY_WAIT;
|
io_state <= BUSY_WAIT;
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end if;
|
end if;
|
|
|
when BUSY_PREP =>
|
when BUSY_PREP =>
|
busy_timer <= BUSY_DELAY;
|
busy_timer <= BUSY_DELAY;
|
if( LCD_Addr = '0' and LCD_Data < 4 )then
|
if( LCD_Addr = '0' and LCD_Data < 4 )then
|
busy_timer <= CLDSP_DELAY;
|
busy_timer <= CLDSP_DELAY;
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end if;
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end if;
|
io_state <= BUSY_WAIT;
|
io_state <= BUSY_WAIT;
|
|
|
when BUSY_WAIT =>
|
when BUSY_WAIT =>
|
if( busy_timer = 0 )then
|
if( busy_timer = 0 )then
|
io_state <= ISSUE_INT;
|
io_state <= ISSUE_INT;
|
if( init_count > 0 )then
|
if( init_count > 0 )then
|
init_count <= init_count - 1;
|
init_count <= init_count - 1;
|
io_state <= FN_JUMP;
|
io_state <= FN_JUMP;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when ISSUE_INT =>
|
when ISSUE_INT =>
|
Interrupt <= '1';
|
Interrupt <= '1';
|
io_state <= IDLE;
|
io_state <= IDLE;
|
|
|
when others => null;
|
when others => null;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Contrast control logic (optional)
|
-- Contrast control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Contrast_Disabled: if( not Use_Contrast )generate
|
Contrast_Disabled: if( not Use_Contrast )generate
|
LCD_CN <= '0';
|
LCD_CN <= '0';
|
end generate;
|
end generate;
|
|
|
Contrast_Enabled: if( Use_Contrast )generate
|
Contrast_Enabled: if( Use_Contrast )generate
|
|
|
U_CN : entity work.vdsm8
|
U_CN : entity work.vdsm8
|
generic map(
|
generic map(
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
DACin => LCD_Contrast,
|
DACin => LCD_Contrast,
|
DACout => LCD_CN
|
DACout => LCD_CN
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Backlight control logic (optional)
|
-- Backlight control logic (optional)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Backlight_Disabled: if( not Use_Backlight )generate
|
Backlight_Disabled: if( not Use_Backlight )generate
|
LCD_BL <= '0';
|
LCD_BL <= '0';
|
end generate;
|
end generate;
|
|
|
Backlight_Enabled: if( Use_Backlight )generate
|
Backlight_Enabled: if( Use_Backlight )generate
|
|
|
U_BL : entity work.vdsm8
|
U_BL : entity work.vdsm8
|
generic map(
|
generic map(
|
Reset_Level => Reset_Level
|
Reset_Level => Reset_Level
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
DACin => LCD_Bright,
|
DACin => LCD_Bright,
|
DACout => LCD_BL
|
DACout => LCD_BL
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
end architecture;
|
end architecture;
|
|
|
