| Line 73... |
Line 73... |
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constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
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constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
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constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Reg_Sel is Open8_Bus.Address(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Wr_Data_q : DATA_TYPE;
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Rd_En : std_logic;
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal User_In : DATA_TYPE;
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal User_Trig : std_logic;
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signal User_Trig : std_logic;
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signal Timer_Int : DATA_TYPE;
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signal Timer_Int : DATA_TYPE;
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signal Timer_Cnt : DATA_TYPE;
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signal Timer_Cnt : DATA_TYPE;
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Line 104... |
signal ADC2_Data : std_logic_vector(13 downto 0);
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signal ADC2_Data : std_logic_vector(13 downto 0);
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signal ADC_Ready : std_logic;
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signal ADC_Ready : std_logic;
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= (others => '0');
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Reg_Sel_q <= "000";
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Wr_En <= '0';
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Rd_En_q <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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User_Trig <= '0';
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User_Trig <= '0';
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Timer_Int <= x"00";
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Timer_Int <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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User_Trig <= '0';
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User_Trig <= '0';
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' )then
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if( Reg_Sel_q = "110" )then
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if( Reg_Sel_q = "110" )then
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Timer_Int <= Wr_Data_q;
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Timer_Int <= Wr_Data_q;
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end if;
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end if;
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if( Reg_Sel_q = "111" )then
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if( Reg_Sel_q = "111" )then
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User_Trig <= '1';
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User_Trig <= '1';
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end if;
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end if;
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end if;
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end if;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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-- Channel 1, Full resolution, lower byte
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-- Channel 1, Full resolution, lower byte
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when "000" =>
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when "000" =>
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Rd_Data <= ADC1_Data(7 downto 0);
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Rd_Data <= ADC1_Data(7 downto 0);
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-- Channel 1, Full resolution, upper byte
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-- Channel 1, Full resolution, upper byte
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