| Line 62... |
Line 62... |
--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 87... |
Line 88... |
Clock_Frequency : real := 100000000.0;
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Clock_Frequency : real := 100000000.0;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- Serial IO
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-- Serial IO
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SDLC_In : in std_logic;
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SDLC_In : in std_logic;
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SDLC_SClk : in std_logic;
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SDLC_SClk : in std_logic;
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Line 113... |
signal Base_Addr_Match : std_logic := '0';
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signal Base_Addr_Match : std_logic := '0';
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alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
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alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
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signal DP_A_Wr_En : std_logic := '0';
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signal DP_A_Wr_En : std_logic := '0';
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alias DP_A_Wr_Data is Open8_Bus.Wr_Data;
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alias DP_A_Wr_Data is Open8_Bus.Wr_Data;
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signal DP_A_Rd_En : std_logic := '0';
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signal DP_A_Rd_En_d : std_logic := '0';
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signal DP_A_Rd_En_q : std_logic := '0';
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signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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alias Reg_Upper_Addr is Open8_Bus.Address(8 downto 1);
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alias Reg_Upper_Addr is Open8_Bus.Address(8 downto 1);
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alias Reg_Lower_Addr is Open8_Bus.Address(0);
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alias Reg_Lower_Addr is Open8_Bus.Address(0);
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Wr_En_d : std_logic := '0';
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signal Reg_Wr_En_q : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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signal DP_B_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_B_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_B_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_B_Wr_Data : DATA_IN_TYPE := x"00";
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-- ***************************************************************************
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-- ***************************************************************************
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- do the lookup before we have to set Rd_Data
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-- do the lookup before we have to set Rd_Data
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Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
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Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
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DP_A_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
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Reg_Wr_En_d <= Base_Addr_Match and
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Open8_Bus.Wr_En and
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Write_Qual;
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DP_A_Wr_En <= Base_Addr_Match and
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Open8_Bus.Wr_En and
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Write_Qual;
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DP_A_Rd_En_d <= Base_Addr_Match and Open8_Bus.Rd_En;
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CPU_IF_proc: process( Reset, Clock )
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CPU_IF_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Addr <= (others => '0');
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Reg_Addr <= (others => '0');
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Reg_Wr_En <= '0';
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Reg_Wr_En_q <= '0';
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Reg_Clk_Sel <= '0';
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Reg_Clk_Sel <= '0';
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Reg_TxS_Sel <= '0';
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Reg_TxS_Sel <= '0';
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DP_A_Rd_En <= '0';
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DP_A_Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Reg_Addr <= Reg_Upper_Addr;
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Reg_Addr <= Reg_Upper_Addr;
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Reg_Sel <= Reg_Lower_Addr;
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Reg_Sel <= Reg_Lower_Addr;
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Reg_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
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Reg_Wr_En_q <= Reg_Wr_En_d;
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Reg_Clk_Sel <= '0';
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Reg_Clk_Sel <= '0';
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Reg_TxS_Sel <= '0';
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Reg_TxS_Sel <= '0';
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if( Reg_Addr = Reg_Sub_Addr )then
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if( Reg_Addr = Reg_Sub_Addr )then
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Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
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Reg_Clk_Sel <= Reg_Wr_En_q and not Reg_Sel;
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Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
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Reg_TxS_Sel <= Reg_Wr_En_q and Reg_Sel;
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end if;
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end if;
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DP_A_Rd_En <= Base_Addr_Match and Open8_Bus.Rd_En;
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DP_A_Rd_En_q <= DP_A_Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( DP_A_Rd_En = '1' )then
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if( DP_A_Rd_En_q = '1' )then
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Rd_Data <= DP_A_Rd_Data;
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Rd_Data <= DP_A_Rd_Data;
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end if;
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end if;
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Interrupt <= RX_Interrupt or TX_Interrupt;
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Interrupt <= RX_Interrupt or TX_Interrupt;
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end if;
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end if;
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