| Line 36... |
Line 36... |
-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- interval write.
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-- interval write.
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 48... |
Line 49... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_sys_timer is
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entity o8_sys_timer is
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generic(
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generic(
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Write_Protect : boolean := FALSE;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_sys_timer is
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architecture behave of o8_sys_timer is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
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signal Wr_En_d : std_logic;
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signal Rd_En_d : std_logic;
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alias Wr_Data is Open8_Bus.Wr_Data;
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constant User_Addr : ADDRESS_TYPE := Address;
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constant User_Addr : ADDRESS_TYPE := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En_d : std_logic;
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Interval : DATA_TYPE := x"00";
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signal Interval : DATA_TYPE := x"00";
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signal Update_Interval : std_logic;
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signal Update_Interval : std_logic;
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signal Timer_Cnt : DATA_TYPE := x"00";
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signal Timer_Cnt : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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-- If the Write_Protect generic is set only allow the memory to be written
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-- if the ISR bit is set. Otherwise, the memory should be read-only
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Write_Protect_On : if( Write_Protect )generate
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and ISR_En;
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end generate;
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Write_Protect_Off : if( not Write_Protect )generate
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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end generate;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Interval <= x"00";
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Interval <= x"00";
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Update_Interval <= '0';
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Update_Interval <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data_d;
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Update_Interval <= Wr_En;
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Update_Interval <= Wr_En_q and Write_Qual;
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' and Write_Qual = '1' )then
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Interval <= Wr_Data_q;
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Interval <= Wr_Data_q;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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if( Rd_En = '1' )then
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if( Rd_En_q = '1' )then
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Rd_Data <= Interval;
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Rd_Data <= Interval;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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