Line 38... |
Line 38... |
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
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-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
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-- change.
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-- change.
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
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-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
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-- conditions instead
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-- conditions instead
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-- Seth Henry 05/23/20 Added the parallel interface
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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Line 60... |
Line 61... |
);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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--
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-- Parallel Interface
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Rx_In : in std_logic
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Vec_Req : in std_logic;
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Vec_Index : in std_logic_vector(5 downto 0);
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Vec_Data : in std_logic_vector(15 downto 0);
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-- Serial Interface
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Vec_Rx : in std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_vector_rx is
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architecture behave of o8_vector_rx is
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Line 93... |
Line 98... |
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signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) :=
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signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) :=
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(others => '0');
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(others => '0');
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signal Rx_Baud_Tick : std_logic;
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signal Rx_Baud_Tick : std_logic;
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signal Rx_In_SR : std_logic_vector(2 downto 0);
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signal Vec_Rx_SR : std_logic_vector(2 downto 0);
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alias Rx_In_MS is Rx_In_SR(2);
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alias Vec_Rx_MS is Vec_Rx_SR(2);
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signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
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signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
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signal RX_Idle : std_logic;
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signal RX_Idle : std_logic;
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signal Rx_Data : DATA_TYPE := x"00";
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signal Rx_Valid : std_logic;
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type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
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type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
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SEND_INTERRUPT );
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SEND_INTERRUPT );
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signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
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signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
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signal Vector_Cmd : DATA_TYPE := x"00";
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signal Vec_Req_SR : std_logic_vector(2 downto 0);
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signal Vector_Arg_LB : DATA_TYPE := x"00";
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alias Vec_Req_MS is Vec_Rx_SR(2);
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signal Vector_Arg_UB : DATA_TYPE := x"00";
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signal Rx_Data : DATA_TYPE := x"00";
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signal Vector_Index : DATA_TYPE := x"00";
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signal Rx_Valid : std_logic;
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signal Vector_Data : ADDRESS_TYPE := x"0000";
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alias Vector_Data_LB is Vector_Data(7 downto 0);
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alias Vector_Data_UB is Vector_Data(15 downto 8);
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Line 128... |
Line 136... |
Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En_q <= Rd_En_d;
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Rd_En_q <= Rd_En_d;
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if( Rd_En_q = '1' )then
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" =>
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when "00" =>
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Rd_Data <= Vector_Cmd;
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Rd_Data <= Vector_Index;
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when "01" =>
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when "01" =>
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Rd_Data <= Vector_Arg_LB;
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Rd_Data <= Vector_Data_LB;
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when "10" =>
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when "10" =>
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Rd_Data <= Vector_Arg_UB;
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Rd_Data <= Vector_Data_UB;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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Line 145... |
Line 153... |
RX_Idle_proc: process( Clock, Reset )
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RX_Idle_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rx_Baud_Cntr <= (others => '0');
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Rx_Baud_Cntr <= (others => '0');
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Rx_Baud_Tick <= '0';
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Rx_Baud_Tick <= '0';
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Rx_In_SR <= (others => '1');
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Vec_Rx_SR <= (others => '1');
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Rx_Idle_Cntr <= (others => '0');
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Rx_Idle_Cntr <= (others => '0');
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Rx_Idle <= '0';
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Rx_Idle <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
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Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
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Rx_Baud_Tick <= '0';
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Rx_Baud_Tick <= '0';
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if( Rx_Baud_Cntr = 0 )then
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if( Rx_Baud_Cntr = 0 )then
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Rx_Baud_Cntr <= FULL_PERIOD;
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Rx_Baud_Cntr <= FULL_PERIOD;
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Rx_Baud_Tick <= '1';
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Rx_Baud_Tick <= '1';
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end if;
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end if;
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Rx_In_SR <= Rx_In_SR(1 downto 0) & Rx_In;
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Vec_Rx_SR <= Vec_Rx_SR(1 downto 0) & Vec_Rx;
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Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
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Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
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if( Rx_In_MS = '0' )then
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if( Vec_Rx_MS = '0' )then
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Rx_Idle_Cntr <= (others => '1');
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Rx_Idle_Cntr <= (others => '1');
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elsif( Rx_Idle_Cntr = 0 )then
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elsif( Rx_Idle_Cntr = 0 )then
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Rx_Idle_Cntr <= (others => '0');
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Rx_Idle_Cntr <= (others => '0');
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end if;
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end if;
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Line 179... |
Line 187... |
)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Rx_In => RX_In,
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RX_In => Vec_Rx,
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--
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--
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Rx_Data => RX_Data,
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Rx_Data => RX_Data,
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Rx_Valid => RX_Valid,
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Rx_Valid => RX_Valid,
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Rx_PErr => open
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Rx_PErr => open
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);
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);
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Vector_RX_proc: process( Clock, Reset )
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Vector_RX_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Vec_Req_SR <= (others => '0');
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Vector_State <= GET_VECTOR_CMD;
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Vector_State <= GET_VECTOR_CMD;
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Vector_Cmd <= x"00";
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Vector_Index <= x"00";
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Vector_Arg_LB <= x"00";
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Vector_Data <= x"0000";
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Vector_Arg_UB <= x"00";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req;
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Interrupt <= '0';
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Interrupt <= '0';
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if( Vec_Req_MS = '1' )then
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Vector_Index <= "00" & Vec_Index;
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Vector_Data <= Vec_Data;
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Interrupt <= '1';
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end if;
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case( Vector_State )is
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case( Vector_State )is
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when GET_VECTOR_CMD =>
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when GET_VECTOR_CMD =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Vector_Cmd <= Rx_Data;
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Vector_Index <= "00" & Rx_Data(5 downto 0);
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Vector_State <= GET_VECTOR_ARG_LB;
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Vector_State <= GET_VECTOR_ARG_LB;
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end if;
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end if;
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when GET_VECTOR_ARG_LB =>
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when GET_VECTOR_ARG_LB =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Vector_Arg_LB <= Rx_Data;
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Vector_Data_LB <= Rx_Data;
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Vector_State <= GET_VECTOR_ARG_UB;
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Vector_State <= GET_VECTOR_ARG_UB;
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end if;
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end if;
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when GET_VECTOR_ARG_UB =>
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when GET_VECTOR_ARG_UB =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Vector_Arg_UB <= Rx_Data;
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Vector_Data_UB <= Rx_Data;
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Vector_State <= SEND_INTERRUPT;
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Vector_State <= SEND_INTERRUPT;
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end if;
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end if;
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when SEND_INTERRUPT =>
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when SEND_INTERRUPT =>
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Interrupt <= '1';
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Interrupt <= '1';
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