URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [execute.c] - Diff between revs 385 and 420

Rev 385	Rev 420
Line 793...	Line 793...

`} /* dumpreg() */`	`} /* dumpreg() */`


`/---------------------------------------------------------------------------/`	`/---------------------------------------------------------------------------/`
	`/*!Trace an instruction`

	`Supports GDB tracing */`
	`/---------------------------------------------------------------------------/`
	`void`
	`trace_instr ()`
	`{`
	`oraddr_t physical_pc;`

	`if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))`
	`{`
	`disassemble_instr (physical_pc);`
	`}`
	`else`
	`{`
	`PRINTF ("INTERNAL SIMULATOR ERROR: no trace available\n");`
	`}`
	`} /* trace_instr () */`


	`/---------------------------------------------------------------------------/`
`/*!Wrapper around real decode_execute function`	`/*!Wrapper around real decode_execute function`

`Some statistics here only`	`Some statistics here only`

`@param[in] current Instruction being executed */`	`@param[in] current Instruction being executed */`
Line 1013...	Line 1034...
`}`	`}`

`/* If we are tracing, dump after each instruction. */`	`/* If we are tracing, dump after each instruction. */`
`if (!runtime.sim.hush)`	`if (!runtime.sim.hush)`
`{`	`{`
`dumpreg ();`	`trace_instr ();`
`}`	`}`

`if (config.vapi.enabled && runtime.vapi.enabled)`	`if (config.vapi.enabled && runtime.vapi.enabled)`
`{`	`{`
`vapi_check ();`	`vapi_check ();`