URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [ddr2_model.v] - Diff between revs 360 and 412

Rev 360	Rev 412
Line 1...	Line 1...
`/****************************************************************************************`	`/****************************************************************************************`
`*`	`*`
`* File Name: ddr2.v`	`* File Name: ddr2_model.v`
`* Version: 5.80`	`* Version: 5.80`
`* Model: BUS Functional`	`* Model: BUS Functional`
`*`	`*`
`* Dependencies: ddr2_parameters.vh`	`* Dependencies: ddr2_parameters.v`
`*`	`*`
`* Description: Micron SDRAM DDR2 (Double Data Rate 2)`	`* Description: Micron SDRAM DDR2 (Double Data Rate 2)`
`*`	`*`
`* Limitation: - doesn't check for average refresh timings`	`* Limitation: - doesn't check for average refresh timings`
`* - positive ck and ck_n edges are used to form internal clock`	`* - positive ck and ck_n edges are used to form internal clock`
Line 135...	Line 135...
`dqs_n,`	`dqs_n,`
`rdqs_n,`	`rdqs_n,`
`odt`	`odt`
`);`	`);`

`include "ddr2_model_parameters.vh"	`include "ddr2_model_parameters.v"

`// text macros`	`// text macros`
`define DQ_PER_DQS DQ_BITS/DQS_BITS	`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)	`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)	`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)