OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [link.ld] - Diff between revs 584 and 623

Only display areas with differences | Details | Blame | View Log

Rev 584	Rev 623
`MEMORY`	`MEMORY`
`{`	`{`
`vectors : ORIGIN = 0x00000000, LENGTH = 0x00001100`	`vectors : ORIGIN = 0x00000000, LENGTH = 0x00001000`
`ram : ORIGIN = 0x00001200, LENGTH = 0x00080000 - 0x00001200`	`ram : ORIGIN = 0x00001000, LENGTH = 0x00080000 - 0x00001000`
`}`	`}`

`SECTIONS`	`SECTIONS`
`{`	`{`
`.vectors :`	`.vectors :`
`{`	`{`
`_vec_start = .;`	`_vec_start = .;`
`*(.vectors)`	`*(.vectors)`
`_vec_end = .;`	`_vec_end = .;`
`} > vectors`	`} > vectors`

`.text ALIGN(4) :`	`.text ALIGN(4) :`
`{`	`{`
`*(.text)`	`*(.text)`
`} > ram`	`} > ram`

`.rodata ALIGN(4) :`	`.rodata ALIGN(4) :`
`{`	`{`
`*(.rodata)`	`*(.rodata)`
`(.rodata.)`	`(.rodata.)`
`} > ram`	`} > ram`

`.icm ALIGN(4) :`	`.icm ALIGN(4) :`
`{`	`{`
`_icm_start = .;`	`_icm_start = .;`
`*(.icm)`	`*(.icm)`
`_icm_end = .;`	`_icm_end = .;`
`} > ram`	`} > ram`

`.data ALIGN(4) :`	`.data ALIGN(4) :`
`{`	`{`
`_dst_beg = .;`	`_dst_beg = .;`
`*(.data)`	`*(.data)`
`_dst_end = .;`	`_dst_end = .;`
`} > ram`	`} > ram`

`.bss ALIGN(4) :`	`.bss ALIGN(4) :`
`{`	`{`
`_bss_beg = .;`	`_bss_beg = .;`
`*(.bss)`	`*(.bss)`
`_bss_end = .;`	`_bss_end = .;`
`} > ram`	`} > ram`

`PROVIDE(_stack_top = 0x00080000);`	`PROVIDE(_stack_top = 0x00080000);`
`}`	`}`

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.