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| Rev 675 |
Rev 799 |
/* Support file for c based tests */
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/* Support file for c based tests */
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "board.h"
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#include "board.h"
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#include "mc.h"
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#include "mc.h"
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.global _stack_top
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.global _stack_top
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.section .vectors, "ax"
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.section .vectors, "ax"
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.org 0x100
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.org 0x100
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_reset_vector:
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_reset_vector:
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l.nop
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l.nop
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l.nop
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l.nop
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l.addi r2,r0,0x0
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
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l.addi r3,r0,0x0
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r8,r0,0x0
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l.addi r9,r0,0x0
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l.addi r9,r0,0x0
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l.addi r10,r0,0x0
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l.addi r10,r0,0x0
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l.addi r11,r0,0x0
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l.addi r11,r0,0x0
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l.addi r12,r0,0x0
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l.addi r12,r0,0x0
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l.addi r13,r0,0x0
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l.addi r13,r0,0x0
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l.addi r14,r0,0x0
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l.addi r14,r0,0x0
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l.addi r15,r0,0x0
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l.addi r15,r0,0x0
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l.addi r16,r0,0x0
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l.addi r16,r0,0x0
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l.addi r17,r0,0x0
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l.addi r17,r0,0x0
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l.addi r18,r0,0x0
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l.addi r18,r0,0x0
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l.addi r19,r0,0x0
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l.addi r19,r0,0x0
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l.addi r20,r0,0x0
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l.addi r20,r0,0x0
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l.addi r21,r0,0x0
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l.addi r21,r0,0x0
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l.addi r22,r0,0x0
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l.addi r22,r0,0x0
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l.addi r23,r0,0x0
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l.addi r23,r0,0x0
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l.addi r24,r0,0x0
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l.addi r24,r0,0x0
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l.addi r25,r0,0x0
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l.addi r25,r0,0x0
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l.addi r26,r0,0x0
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l.addi r26,r0,0x0
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l.addi r27,r0,0x0
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l.addi r27,r0,0x0
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l.addi r28,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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l.movhi r3,hi(_start)
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.org 0x200
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.org 0x200
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_except_200:
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_except_200:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x200
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l.addi r3, r0, 0x200
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0x300
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.org 0x300
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_except_300:
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_except_300:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x300
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l.addi r3, r0, 0x300
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0x400
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.org 0x400
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_except_400:
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_except_400:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x400
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l.addi r3, r0, 0x400
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0x500
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.org 0x500
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_except_500:
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_except_500:
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l.nop
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l.nop
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l.j vPortTickHandler
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l.j vPortTickHandler
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l.nop
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l.nop
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.org 0x600
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.org 0x600
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_except_600:
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_except_600:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x600
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l.addi r3, r0, 0x600
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0x700
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.org 0x700
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_except_700:
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_except_700:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x700
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l.addi r3, r0, 0x700
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0x800
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.org 0x800
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_except_800:
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_except_800:
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l.nop
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l.nop
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l.j vPortExtIntHandler
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l.j vPortExtIntHandler
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l.nop
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l.nop
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.org 0x900
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.org 0x900
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_except_900:
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_except_900:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0x900
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l.addi r3, r0, 0x900
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0xa00
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.org 0xa00
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_except_a00:
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_except_a00:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0xa00
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l.addi r3, r0, 0xa00
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0xb00
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.org 0xb00
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_except_b00:
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_except_b00:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0xb00
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l.addi r3, r0, 0xb00
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0xc00
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.org 0xc00
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_except_c00:
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_except_c00:
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.global vPortSystemCall
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.global vPortSystemCall
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l.nop
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l.nop
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l.j vPortSystemCall
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l.j vPortSystemCall
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l.nop
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l.nop
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.org 0xd00
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.org 0xd00
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_except_d00:
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_except_d00:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0xd00
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l.addi r3, r0, 0xd00
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0xe00
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.org 0xe00
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_except_e00:
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_except_e00:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0xe00
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l.addi r3, r0, 0xe00
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.org 0xf00
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.org 0xf00
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_except_f00:
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_except_f00:
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l.nop
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l.nop
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l.sw -4(r1), r3
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l.sw -4(r1), r3
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l.addi r3, r0, 0xf00
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l.addi r3, r0, 0xf00
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l.sw -260(r1), r3
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l.sw -260(r1), r3
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l.lwz r3, -4(r1)
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l.lwz r3, -4(r1)
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l.j vPortMiscIntHandler
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l.j vPortMiscIntHandler
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l.nop
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l.nop
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.section .text
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.section .text
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_start:
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_start:
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.if IC | DC
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/* Flush IC and/or DC */
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l.addi r10,r0,0
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l.addi r11,r0,0
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l.addi r12,r0,0
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.if IC
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l.addi r11,r0,IC_SIZE
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.endif
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.if DC
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l.addi r12,r0,DC_SIZE
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.endif
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l.sfleu r12,r11
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l.bf loop
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l.nop
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l.add r11,r0,r12
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loop:
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.if IC
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l.mtspr r0,r10,SPR_ICBIR
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.endif
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.if DC
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l.mtspr r0,r10,SPR_DCBIR
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.endif
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l.sfne r10,r11
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l.bf loop
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l.addi r10,r10,16
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/* Enable IC and/or DC */
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l.addi r10,r0,(SPR_SR_SM)
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.if IC
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l.ori r10,r10,(SPR_SR_ICE)
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.endif
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.if DC
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l.ori r10,r10,(SPR_SR_DCE)
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.endif
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l.mtspr r0,r10,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.endif
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/* Set stack pointer */
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/* Set stack pointer */
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l.movhi r1, hi(_stack_top)
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l.movhi r1, hi(_stack_top)
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l.ori r1, r1, lo(_stack_top)
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l.ori r1, r1, lo(_stack_top)
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/* clear BSS */
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/* clear BSS */
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l.movhi r2, hi(_bss_beg)
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l.movhi r2, hi(_bss_beg)
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l.ori r2, r2, lo(_bss_beg)
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l.ori r2, r2, lo(_bss_beg)
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l.movhi r3, hi(_bss_end)
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l.movhi r3, hi(_bss_end)
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l.ori r3, r2, lo(_bss_end)
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l.ori r3, r2, lo(_bss_end)
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1:
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1:
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l.sfeq r2, r3
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l.sfeq r2, r3
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l.bf __main
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l.bf __main
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l.nop
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l.nop
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l.sw 0x0(r2), r0
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l.sw 0x0(r2), r0
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l.addi r2, r2, 0x4
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l.addi r2, r2, 0x4
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l.j 1b
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l.j 1b
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l.nop
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l.nop
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/* Jump to main */
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/* Jump to main */
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__main:
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__main:
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l.movhi r2, hi(_main)
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l.movhi r2, hi(_main)
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l.ori r2, r2, lo(_main)
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l.ori r2, r2, lo(_main)
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l.jr r2
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l.jr r2
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l.nop
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l.nop
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