//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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interface
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interface spi_if #(N=1);
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spi_if();
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import uvm_pkg::*;
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import uvm_pkg::*;
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`include "uvm_macros.svh"
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`include "uvm_macros.svh"
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import tb_spi_pkg::*;
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import tb_spi_pkg::*;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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logic sclk;
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logic sclk;
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logic ss_n;
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logic [N-1:0] ss_n;
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logic mosi;
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logic mosi;
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logic miso;
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logic miso;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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time period = 40ns;
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time period = 40ns;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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default clocking cb_rise @(posedge sclk);
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default clocking cb_rise @(posedge sclk);
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inout ss_n;
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inout ss_n;
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output mosi;
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output mosi;
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input miso;
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input miso;
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endclocking
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endclocking
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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clocking cb_fall @(negedge sclk);
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clocking cb_fall @(negedge sclk);
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inout ss_n;
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inout ss_n;
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output mosi;
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output mosi;
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input miso;
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input miso;
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endclocking
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endclocking
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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task zero_cycle_delay;
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task zero_cycle_delay;
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##0;
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##0;
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endtask: zero_cycle_delay
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endtask: zero_cycle_delay
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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endinterface
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endinterface
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